src/mem/ruby/config/MI_example-homogeneous.rb

   1 #!/usr/bin/ruby
   2 #
   3 #  Creates a homogeneous CMP system with a single unified cache per
   4 #  core and a crossbar network.  Uses the default parameters listed
   5 #  below, which can be overridden if a wrapper script sets the hash
   6 #  libruby_args.
   7 #
   8
   9 require "cfg.rb"
  10
  11 RubySystem.reset
  12
  13 # default values
  14
  15 num_cores = 2
  16 l1_cache_size_kb = 32
  17 l1_cache_assoc = 8
  18 l1_cache_latency = 1
  19 num_memories = 2
  20 memory_size_mb = 1024
  21 num_dma = 1
  22 protocol = "MI_example"
  23
  24 # check for overrides
  25
  26
  27 for i in 0..$*.size-1 do
  28   if $*[i] == "-c"
  29     protocol = $*[i+1]
  30     i = i+1
  31   elsif $*[i] == "-p"
  32     num_cores = $*[i+1].to_i
  33     i = i+1
  34   elsif $*[i] == "-m"
  35     num_memories = $*[i+1].to_i
  36     i = i+1
  37   elsif $*[i] == "-s"
  38     memory_size_mb = $*[i+1].to_i
  39     i = i + 1
  40   end
  41 end
  42
  43 net_ports = Array.new
  44 iface_ports = Array.new
  45
  46 assert(protocol == "MI_example", __FILE__ + " cannot be used with protocol " + protocol)
  47
  48 require protocol+".rb"
  49
  50 num_cores.times { |n|
  51   cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_kb, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU")
  52   sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache)
  53   iface_ports << sequencer
  54   net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s,
  55                                    "L1Cache",
  56                                    cache,
  57                                    sequencer)
  58 }
  59 num_memories.times { |n|
  60   directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
  61   memory_control = MemoryControl.new("MemoryControl_"+n.to_s)
  62   net_ports << MI_example_DirectoryController.new("DirectoryController_"+n.to_s,
  63                                        "Directory",
  64                                        directory, memory_control)
  65 }
  66 num_dma.times { |n|
  67   dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
  68   iface_ports << dma_sequencer
  69   net_ports << MI_example_DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer)
  70 }
  71
  72 topology = CrossbarTopology.new("theTopology", net_ports)
  73 on_chip_net = Network.new("theNetwork", topology)
  74
  75 RubySystem.init(iface_ports, on_chip_net)