src/mem/ruby/config/MI_example.rb

   1
   2 require "util.rb"
   3
   4 class MI_example_CacheController < L1CacheController
   5   attr :cache
   6   def initialize(obj_name, mach_type, cache, sequencer)
   7     super(obj_name, mach_type, [cache], sequencer)
   8     @cache = cache
   9   end
  10   def argv()
  11     vec = super()
  12     vec += " cache " + @cache.obj_name
  13     vec += " issue_latency "+issue_latency.to_s
  14     vec += " cache_response_latency "+cache_response_latency.to_s
  15   end
  16
  17 end
  18
  19 class MI_example_DirectoryController < DirectoryController
  20   def initialize(obj_name, mach_type, directory, memory_control)
  21     super(obj_name, mach_type, directory, memory_control)
  22   end
  23   def argv()
  24     vec = super()
  25     vec += " directory_latency "+directory_latency.to_s
  26     vec += " dma_select_low_bit "+log_int(RubySystem.block_size_bytes).to_s
  27     vec += " dma_select_num_bits "+log_int(NetPort.totalOfType("DMA")).to_s
  28   end
  29 end
  30
  31 class MI_example_DMAController < DMAController
  32   def initialize(obj_name, mach_type, dma_sequencer)
  33     super(obj_name, mach_type, dma_sequencer)
  34   end
  35   def argv()
  36     vec = super
  37     vec += " request_latency "+request_latency.to_s
  38   end
  39 end