6 class MOESI_CMP_directory_L1CacheController
< L1CacheController
8 attr
:num_l2_controllers
9 def initialize(obj_name
, mach_type
, icache
, dcache
, sequencer
, num_l2_controllers
)
10 super(obj_name
, mach_type
, [icache
, dcache
], sequencer
)
13 @num_l2_controllers = num_l2_controllers
16 num_select_bits
= log_int(num_l2_controllers
)
17 num_block_bits
= log_int(RubySystem
.block_size_bytes
)
19 l2_select_low_bit
= num_block_bits
22 vec
+= " icache " + @icache.obj_name
23 vec
+= " dcache " + @dcache.obj_name
24 vec
+= " request_latency "+request_latency().to_s
25 vec
+= " l2_select_low_bit " + l2_select_low_bit
.to_s
26 vec
+= " l2_select_num_bits " + num_select_bits
.to_s
31 class MOESI_CMP_directory_L2CacheController
< CacheController
33 def initialize(obj_name
, mach_type
, cache
)
34 super(obj_name
, mach_type
, [cache
])
39 vec
+= " cache " + @cache.obj_name
40 vec
+= " request_latency "+request_latency().to_s
41 vec
+= " response_latency "+response_latency().to_s
47 class MOESI_CMP_directory_DirectoryController
< DirectoryController
48 def initialize(obj_name
, mach_type
, directory
, memory_control
)
49 super(obj_name
, mach_type
, directory
, memory_control
)
53 vec
+= " directory_latency "+directory_latency
.to_s
59 class MOESI_CMP_directory_DMAController
< DMAController
60 def initialize(obj_name
, mach_type
, dma_sequencer
)
61 super(obj_name
, mach_type
, dma_sequencer
)
65 vec
+= " request_latency "+request_latency
.to_s
66 vec
+= " response_latency "+response_latency
.to_s