src/mem/ruby/config/config.hh

   1
   2 // FOR MOESI_CMP_token
   3 //PARAM_BOOL(  FilteringEnabled, false, false );
   4 //PARAM_BOOL(  DistributedPersistentEnabled, true, false );
   5 //PARAM_BOOL(  DynamicTimeoutEnabled, true, false );
   6 //PARAM( RetryThreshold, 1, false );
   7 //PARAM( FixedTimeoutLatency, 300, false );
   8
   9 //PARAM( TraceWarmupLength, 1000000, false );
  10
  11 //PARAM( callback_counter, 0, false );
  12 //PARAM( NUM_COMPLETIONS_BEFORE_PASS, 0, false );
  13
  14 //PARAM( tester_length, 0, false );
  15 //PARAM( synthetic_locks, 2048, false );
  16 //PARAM( think_time, 5, false );
  17 //PARAM( wait_time, 5, false );
  18 //PARAM( hold_time, 5, false );
  19 //PARAM( deterministic_addrs, 1, false );
  20 //PARAM_STRING( SpecifiedGenerator, "DetermInvGenerator", false );
  21
  22 // For debugging purposes, one can enable a trace of all the protocol
  23 // state machine changes. Unfortunately, the code to generate the
  24 // trace is protocol specific. To enable the code for some of the
  25 // standard protocols,
  26 //   1. change "PROTOCOL_DEBUG_TRACE = true"
  27 //   2. enable debug in Makefile
  28 //   3. use the "--start 1" command line parameter or
  29 //      "g_debug_ptr->setDebugTime(1)" to beging the following to set the
  30 //      debug begin time
  31 //
  32 // this use to be ruby/common/Global.hh
  33
  34 //PARAM_BOOL(  ProtocolDebugTrace, true, false );
  35 // a string for filtering debugging output (for all g_debug vars see Debug.hh)
  36 //PARAM_STRING( DEBUG_FILTER_STRING, "", false );
  37 // filters debugging messages based on priority (low, med, high)
  38 //PARAM_STRING( DEBUG_VERBOSITY_STRING, "", false );
  39 // filters debugging messages based on a ruby time
  40 //PARAM_ULONG( DEBUG_START_TIME, 0, false );
  41 // sends debugging messages to a output filename
  42 //PARAM_STRING( DEBUG_OUTPUT_FILENAME, "", false );
  43
  44 //PARAM_BOOL( ProfileHotLines, false, false );
  45
  46 // PROFILE_ALL_INSTRUCTIONS is used if you want Ruby to profile all instructions executed
  47 // The following need to be true for this to work correctly:
  48 // 1. Disable istc and dstc for this simulation run
  49 // 2. Add the following line to the object "sim" in the checkpoint you run from:
  50 //      instruction_profile_line_size: 4
  51 // This is used to have simics report back all instruction requests
  52
  53 // For more details on how to find out how to interpret the output physical instruction
  54 // address, please read the document in the simics-howto directory
  55 //PARAM_BOOL( ProfileAllInstructions, false, false );
  56
  57 // Set the following variable to true if you want a complete trace of
  58 // PCs (physical address of program counters, with executing processor IDs)
  59 // to be printed to stdout. Make sure to direct the simics output to a file.
  60 // Otherwise, the run will take a really long time!
  61 // A long run may write a file that can exceed the OS limit on file length
  62 //PARAM_BOOL( PRINT_INSTRUCTION_TRACE, false, false );
  63 //PARAM( DEBUG_CYCLE, 0, false );
  64
  65 // Make the entire memory system perfect
  66 //PARAM_BOOL( PERFECT_MEMORY_SYSTEM, false, false );
  67 //PARAM( PERFECT_MEMORY_SYSTEM_LATENCY, 0, false );
  68
  69 // *********************************************
  70 // SYSTEM PARAMETERS
  71 // *********************************************
  72
  73 //PARAM( NumberOfChips, 1, false );
  74 //PARAM( NumberOfCores, 2, false );
  75 //PARAM_ARRAY( NumberOfCoresPerChip, int, m_NumberOfChips, 2, false);
  76
  77 // *********************************************
  78 // CACHE PARAMETERS
  79 // *********************************************
  80
  81 //PARAM( NumberOfCaches, m_NumberOfCores, false );
  82 //PARAM( NumberOfCacheLevels, 1, false );
  83 /* this returns the number of discrete CacheMemories per level (i.e. a split L1 counts for 2) */
  84 //PARAM_ARRAY( NumberOfCachesPerLevel, int, m_NumberOfCacheLevels, m_NumberOfCores, false );   // this is the number of discrete caches if the level is private
  85                                                                                              // or the number of banks if the level is shared
  86 //PARAM( CacheIDFromParams, 1, true );                                                         // returns a unique CacheID from the parameters (level, num, split_type)
  87 //PARAM_ARRAY( CacheLatency, int, m_NumberOfCaches, 1, false );                                // returns the latency for cache, indexed by CacheID
  88 //PARAM_ARRAY( CacheSplitType, string, m_NumberOfCaches, "unified", false );                   // returns "data", "instruction", or "unified", indexed by CacheID
  89 //PARAM_ARRAY( CacheType, string, m_NumberOfCaches, "SetAssociative", false );                 // returns the type of a cache, indexed by CacheID
  90 //PARAM_ARRAY( CacheAssoc, int, m_NumberOfCaches, 4, false );                                  // returns the cache associativity, indexed by CacheID
  91 //PARAM_ARRAY( NumberOfCacheSets, int, m_NumberOfCaches, 256, false );                         // returns the number of cache sets, indexed by CacheID
  92 //PARAM_ARRAY( NumberOfCacheSetBits, int, m_NumberOfCaches, log_int(256), false );             // returns the number of cache set bits, indexed by CacheID
  93 //PARAM_ARRAY( CacheReplacementPolicy, string, m_NumberOfCaches, "PSEUDO_LRU", false );        // other option is "LRU"
  94
  95 //PARAM( DataBlockBytes, 64, false );
  96 //PARAM( DataBlockBits, log_int(m_DataBlockBytes), false);
  97
  98 // ********************************************
  99 // MEMORY PARAMETERS
 100 // ********************************************
 101
 102 //PARAM_ARRAY( NumberOfControllersPerType, int, m_NumberOfCacheLevels+2, m_NumberOfCores, false);
 103 //PARAM_ARRAY2D( NumberOfControllersPerTypePerChip, int, m_NumberOfCacheLevels+2, m_NumberOfChips, m_NumberOfCores, false);
 104
 105 // ********************************************
 106 // DMA CONTROLLER PARAMETERS
 107 // ********************************************
 108
 109 //PARAM( NumberOfDMA, 1, false );
 110 //PARAM_ARRAY( NumberOfDMAPerChip, int, m_NumberOfChips, 1, false);
 111 //PARAM_ARRAY( ChipNumFromDMAVersion, int, m_NumberOfDMA, 0, false );
 112
 113 //PARAM_ULONG( MemorySizeBytes, 4294967296, false );
 114 //PARAM_ULONG( MemorySizeBits, 32, false);
 115
 116 //PARAM( NUM_PROCESSORS, 0, false );
 117 //PARAM( NUM_L2_BANKS, 0, false );
 118 //PARAM( NUM_MEMORIES, 0, false );
 119 //PARAM( ProcsPerChip, 1, false );
 120
 121 // The following group of parameters are calculated.  They must
 122 // _always_ be left at zero.
 123 //PARAM( NUM_CHIPS, 0, false );
 124 //PARAM( NUM_CHIP_BITS, 0, false );
 125 //PARAM( MEMORY_SIZE_BITS, 0, false );
 126 //PARAM( DATA_BLOCK_BITS, 0, false );
 127 //PARAM( PAGE_SIZE_BITS, 0, false );
 128 //PARAM( NUM_PROCESSORS_BITS, 0, false );
 129 //PARAM( PROCS_PER_CHIP_BITS, 0, false );
 130 //PARAM( NUM_L2_BANKS_BITS, 0, false );
 131 //PARAM( NUM_L2_BANKS_PER_CHIP_BITS, 0, false );
 132 //PARAM( NUM_L2_BANKS_PER_CHIP, 0, false );
 133 //PARAM( NUM_MEMORIES_BITS, 0, false );
 134 //PARAM( NUM_MEMORIES_PER_CHIP, 0, false );
 135 //PARAM( MEMORY_MODULE_BITS, 0, false );
 136 //PARAM_ULONG( MEMORY_MODULE_BLOCKS, 0, false );
 137
 138 // TIMING PARAMETERS
 139 //PARAM( DIRECTORY_CACHE_LATENCY, 6, false );
 140
 141 //PARAM( NULL_LATENCY, 1, false );
 142 //PARAM( ISSUE_LATENCY, 2, false );
 143 //PARAM( CACHE_RESPONSE_LATENCY, 12, false );
 144 //PARAM( L2_RESPONSE_LATENCY, 6, false );
 145 //PARAM( L2_TAG_LATENCY, 6, false );
 146 //PARAM( L1_RESPONSE_LATENCY, 3, false );
 147
 148 //PARAM( MEMORY_RESPONSE_LATENCY_MINUS_2, 158, false );
 149 //PARAM( DirectoryLatency, 6, false );
 150
 151 //PARAM( NetworkLinkLatency, 1, false );
 152 //PARAM( COPY_HEAD_LATENCY, 4, false );
 153 //PARAM( OnChipLinkLatency, 1, false );
 154 //PARAM( RecycleLatency, 10, false );
 155 //PARAM( L2_RECYCLE_LATENCY, 5, false );
 156 //PARAM( TIMER_LATENCY, 10000, false );
 157 //PARAM( TBE_RESPONSE_LATENCY, 1, false );
 158 //PARAM_BOOL(  PERIODIC_TIMER_WAKEUPS, true, false );
 159
 160 // constants used by CMP protocols
 161 //PARAM( L1_REQUEST_LATENCY, 2, false );
 162 //PARAM( L2_REQUEST_LATENCY, 4, false );
 163 //PARAM_BOOL( SINGLE_ACCESS_L2_BANKS, true, false ); // hack to simulate multi-cycle L2 bank accesses
 164
 165 // Ruby cycles between when a sequencer issues a miss it arrives at
 166 // the L1 cache controller
 167 //PARAM( SequencerToControllerLatency, 4, false );
 168
 169 // Number of transitions each controller state machines can complete per cycle
 170 //PARAM( L1CacheTransitionsPerCycle, 32, false );
 171 //PARAM( L2CACHE_TRANSITIONS_PER_RUBY_CYCLE, 32, false );
 172 //PARAM( DirectoryTransitionsPerCycle, 32, false );
 173 //PARAM( DMATransitionsPerCycle, 1, false );
 174
 175 // Number of TBEs available for demand misses, prefetches, and replacements
 176 //PARAM( NumberOfTBEs, 128, false );
 177 //PARAM( NumberOfL1TBEs, 32, false );
 178 //PARAM( NumberOfL2TBEs, 32, false );
 179
 180 // NOTE: Finite buffering allows us to simulate a wormhole routed network
 181 // with idealized flow control.  All message buffers within the network (i.e.
 182 // the switch's input and output buffers) are set to the size specified below
 183 // by the PROTOCOL_BUFFER_SIZE
 184 //PARAM_BOOL( FiniteBuffering, false, false );
 185 //PARAM( FiniteBufferSize, 3, false ); // Zero is unbounded buffers
 186 // Number of requests buffered between the sequencer and the L1 conroller
 187 // This can be more accurately simulated in Opal, therefore it's set to an
 188 // infinite number
 189 // Only effects the simualtion when FINITE_BUFFERING is enabled
 190 //PARAM( ProcessorBufferSize, 10, false );
 191 // The PROTOCOL_BUFFER_SIZE limits the size of all other buffers connecting to
 192 // Controllers.  Controlls the number of request issued by the L2 HW Prefetcher
 193 //PARAM( ProtocolBufferSize, 32, false );
 194
 195 // NETWORK PARAMETERS
 196
 197 // Network Topology: See TopologyType in external.sm for valid values
 198 //PARAM_STRING( NetworkTopology, "PT_TO_PT", false );
 199
 200 // Cache Design specifies file prefix for topology
 201 //PARAM_STRING( CacheDesign, "NUCA", false );
 202
 203 //PARAM( EndpointBandwidth, 10000, false );
 204 //PARAM_BOOL( AdaptiveRouting, true, false );
 205 //PARAM( NumberOfVirtualNetworks, 6, false );
 206 //PARAM( FanOutDegree, 4, false );
 207 //PARAM_BOOL( PrintTopology, true, false );
 208
 209 // Princeton Network (Garnet)
 210 //PARAM_BOOL( UsingGarnetNetwork, true, false );
 211 //PARAM_BOOL( UsingDetailNetwork, false, false );
 212 //PARAM_BOOL( UsingNetworkTesting, false, false );
 213 //PARAM( FlitSize, 16, false );
 214 //PARAM( NumberOfPipeStages, 4, false );
 215 //PARAM( VCSPerClass, 4, false );
 216 //PARAM( BufferSize, 4, false );
 217
 218 // MemoryControl:
 219 //PARAM( MEM_BUS_CYCLE_MULTIPLIER, 10, false );
 220 //PARAM( BANKS_PER_RANK, 8, false );
 221 //PARAM( RANKS_PER_DIMM, 2, false );
 222 //PARAM( DIMMS_PER_CHANNEL, 2, false );
 223 //PARAM( BANK_BIT_0, 8, false );
 224 //PARAM( RANK_BIT_0, 11, false );
 225 //PARAM( DIMM_BIT_0, 12, false );
 226 //PARAM( BANK_QUEUE_SIZE, 12, false );
 227 //PARAM( BankBusyTime, 11, false );
 228 //PARAM( RANK_RANK_DELAY, 1, false );
 229 //PARAM( READ_WRITE_DELAY, 2, false );
 230 //PARAM( BASIC_BUS_BUSY_TIME, 2, false );
 231 //PARAM( MEM_CTL_LATENCY, 12, false );
 232 //PARAM( REFRESH_PERIOD, 1560, false );
 233 //PARAM( TFAW, 0, false );
 234 //PARAM( MEM_RANDOM_ARBITRATE, 0, false );
 235 //PARAM( MEM_FIXED_DELAY, 0, false );
 236