2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Description: The Network class is the base class for classes that
33 * implement the interconnection network between components
34 * (processor/cache components and memory/directory components). The
35 * interconnection network as described here is not a physical
36 * network, but a programming concept used to implement all
37 * communication between components. Thus parts of this 'network'
38 * will model the on-chip connections between cache controllers and
39 * directory controllers as well as the links between chip and network
48 #include "mem/ruby/common/Global.hh"
49 #include "mem/ruby/system/NodeID.hh"
50 #include "mem/protocol/MessageSizeType.hh"
51 #include "mem/ruby/system/System.hh"
52 #include "sim/sim_object.hh"
53 #include "params/RubyNetwork.hh"
60 class Network : public SimObject {
63 typedef RubyNetworkParams Params;
64 Network(const Params *p);
71 int getBufferSize() { return m_buffer_size; }
72 int getNumberOfVirtualNetworks() { return m_virtual_networks; }
73 int getEndpointBandwidth() { return m_endpoint_bandwidth; }
74 bool getAdaptiveRouting() {return m_adaptive_routing; }
75 int getLinkLatency() { return m_link_latency; }
76 int MessageSizeType_to_int(MessageSizeType size_type);
79 // returns the queue requested for the given component
80 virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered, int netNumber) = 0;
81 virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int netNumber) = 0;
82 virtual const Vector<Throttle*>* getThrottles(NodeID id) const { return NULL; }
84 virtual int getNumNodes() {return 1;}
86 virtual void makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) = 0;
87 virtual void makeInLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration) = 0;
88 virtual void makeInternalLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) = 0;
90 virtual void reset() = 0;
92 virtual void printStats(ostream& out) const = 0;
93 virtual void clearStats() = 0;
94 virtual void printConfig(ostream& out) const = 0;
95 virtual void print(ostream& out) const = 0;
100 // Private copy constructor and assignment operator
101 Network(const Network& obj);
102 Network& operator=(const Network& obj);
104 // Data Members (m_ prefix)
108 int m_virtual_networks;
110 int m_endpoint_bandwidth;
111 Topology* m_topology_ptr;
112 bool m_adaptive_routing;
114 int m_control_msg_size;
118 // Output operator declaration
119 ostream& operator<<(ostream& out, const Network& obj);
121 // ******************* Definitions *******************
123 // Output operator definition
125 ostream& operator<<(ostream& out, const Network& obj)