MEM: Introduce the master/slave port sub-classes in C++
[gem5.git] / src / mem / ruby / network / Network.py
1 # Copyright (c) 2009 Advanced Micro Devices, Inc.
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15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27 # Authors: Steve Reinhardt
28 # Brad Beckmann
29
30 from m5.params import *
31 from m5.SimObject import SimObject
32 from BasicLink import BasicLink
33
34 class Topology(SimObject):
35 type = 'Topology'
36 description = Param.String("Not Specified",
37 "the name of the imported topology module")
38 ext_links = VectorParam.BasicExtLink("Links to external nodes")
39 int_links = VectorParam.BasicIntLink("Links between internal nodes")
40 routers = VectorParam.BasicRouter("Network routers")
41 print_config = Param.Bool(False,
42 "display topology config in the stats file")
43
44 class RubyNetwork(SimObject):
45 type = 'RubyNetwork'
46 cxx_class = 'Network'
47 abstract = True
48 number_of_virtual_networks = Param.Int(10, "");
49 topology = Param.Topology("");
50 control_msg_size = Param.Int(8, "");
51 ruby_system = Param.RubySystem("");