2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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30 * The topology here is configurable; it can be a hierachical (default
31 * one) or a 2D torus or a 2D torus with half switches killed. I think
32 * all input port has a one-input-one-output switch connected just to
33 * control and bandwidth, since we don't control bandwidth on input
34 * ports. Basically, the class has a vector of nodes and edges. First
35 * 2*m_nodes elements in the node vector are input and output
36 * ports. Edges are represented in two vectors of src and dest
37 * nodes. All edges have latency.
40 #ifndef __MEM_RUBY_NETWORK_TOPOLOGY_HH__
41 #define __MEM_RUBY_NETWORK_TOPOLOGY_HH__
47 #include "mem/protocol/LinkDirection.hh"
48 #include "mem/ruby/common/TypeDefines.hh"
49 #include "mem/ruby/network/BasicLink.hh"
54 typedef std::vector<std::vector<int> > Matrix;
59 LinkDirection direction;
62 typedef std::map<std::pair<int, int>, LinkEntry> LinkMap;
67 Topology(uint32_t num_routers, std::vector<BasicExtLink *> ext_links,
68 std::vector<BasicIntLink *> int_links);
70 uint32_t numSwitches() const { return m_number_of_switches; }
71 void createLinks(Network *net, bool isReconfiguration);
72 void print(std::ostream& out) const { out << "[Topology]"; }
75 void addLink(SwitchID src, SwitchID dest, BasicLink* link,
77 void makeLink(Network *net, SwitchID src, SwitchID dest,
78 const NetDest& routing_table_entry,
79 bool isReconfiguration);
82 uint32_t m_number_of_switches;
84 std::vector<BasicExtLink*> m_ext_link_vector;
85 std::vector<BasicIntLink*> m_int_link_vector;
87 Matrix m_component_latencies;
88 Matrix m_component_inter_switches;
94 operator<<(std::ostream& out, const Topology& obj)
101 #endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__