2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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6 * modification, are permitted provided that the following conditions are
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30 * The topology here is configurable; it can be a hierachical (default
31 * one) or a 2D torus or a 2D torus with half switches killed. I think
32 * all input port has a one-input-one-output switch connected just to
33 * control and bandwidth, since we don't control bandwidth on input
34 * ports. Basically, the class has a vector of nodes and edges. First
35 * 2*m_nodes elements in the node vector are input and output
36 * ports. Edges are represented in two vectors of src and dest
37 * nodes. All edges have latency.
40 #ifndef __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
41 #define __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
47 #include "mem/protocol/LinkDirection.hh"
48 #include "mem/ruby/common/Global.hh"
49 #include "mem/ruby/system/NodeID.hh"
50 #include "params/Topology.hh"
51 #include "sim/sim_object.hh"
56 typedef std::vector<std::vector<int> > Matrix;
61 LinkDirection direction;
64 typedef std::map<std::pair<int, int>, LinkEntry> LinkMap;
66 class Topology : public SimObject
69 typedef TopologyParams Params;
70 Topology(const Params *p);
71 virtual ~Topology() {}
72 const Params *params() const { return (const Params *)_params; }
75 int numSwitches() const { return m_number_of_switches; }
76 void createLinks(Network *net, bool isReconfiguration);
78 void initNetworkPtr(Network* net_ptr);
80 const std::string getName() { return m_name; }
81 void printStats(std::ostream& out) const;
83 void printConfig(std::ostream& out) const;
84 void print(std::ostream& out) const { out << "[Topology]"; }
87 void addLink(SwitchID src, SwitchID dest, BasicLink* link,
89 void makeLink(Network *net, SwitchID src, SwitchID dest,
90 const NetDest& routing_table_entry,
91 bool isReconfiguration);
93 std::string getDesignStr();
94 // Private copy constructor and assignment operator
95 Topology(const Topology& obj);
96 Topology& operator=(const Topology& obj);
101 int m_number_of_switches;
103 std::vector<AbstractController*> m_controller_vector;
104 std::vector<BasicExtLink*> m_ext_link_vector;
105 std::vector<BasicIntLink*> m_int_link_vector;
107 Matrix m_component_latencies;
108 Matrix m_component_inter_switches;
111 std::vector<BasicRouter*> m_router_vector;
115 operator<<(std::ostream& out, const Topology& obj)
122 #endif // __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__