src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc

   1 /*
   2  * Copyright (c) 2008 Princeton University
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Niket Agarwal
  29  */
  30
  31 #include "base/stl_helpers.hh"
  32 #include "mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh"
  33 #include "mem/ruby/network/garnet/fixed-pipeline/Router_d.hh"
  34
  35 using namespace std;
  36 using m5::stl_helpers::deletePointers;
  37
  38 InputUnit_d::InputUnit_d(int id, Router_d *router) : Consumer(router)
  39 {
  40     m_id = id;
  41     m_router = router;
  42     m_num_vcs = m_router->get_num_vcs();
  43     m_vc_per_vnet = m_router->get_vc_per_vnet();
  44
  45     m_num_buffer_reads.resize(m_num_vcs/m_vc_per_vnet);
  46     m_num_buffer_writes.resize(m_num_vcs/m_vc_per_vnet);
  47     for (int i = 0; i < m_num_buffer_reads.size(); i++) {
  48         m_num_buffer_reads[i] = 0;
  49         m_num_buffer_writes[i] = 0;
  50     }
  51
  52     creditQueue = new flitBuffer_d();
  53     // Instantiating the virtual channels
  54     m_vcs.resize(m_num_vcs);
  55     for (int i=0; i < m_num_vcs; i++) {
  56         m_vcs[i] = new VirtualChannel_d(i);
  57     }
  58 }
  59
  60 InputUnit_d::~InputUnit_d()
  61 {
  62     delete creditQueue;
  63     deletePointers(m_vcs);
  64 }
  65
  66 void
  67 InputUnit_d::wakeup()
  68 {
  69     flit_d *t_flit;
  70     if (m_in_link->isReady(m_router->curCycle())) {
  71
  72         t_flit = m_in_link->consumeLink();
  73         int vc = t_flit->get_vc();
  74
  75         if ((t_flit->get_type() == HEAD_) ||
  76            (t_flit->get_type() == HEAD_TAIL_)) {
  77
  78             assert(m_vcs[vc]->get_state() == IDLE_);
  79             // Do the route computation for this vc
  80             m_router->route_req(t_flit, this, vc);
  81
  82             m_vcs[vc]->set_enqueue_time(m_router->curCycle());
  83         } else {
  84             t_flit->advance_stage(SA_, m_router->curCycle() + Cycles(1));
  85             m_router->swarb_req();
  86         }
  87         // write flit into input buffer
  88         m_vcs[vc]->insertFlit(t_flit);
  89
  90         int vnet = vc/m_vc_per_vnet;
  91         // number of writes same as reads
  92         // any flit that is written will be read only once
  93         m_num_buffer_writes[vnet]++;
  94         m_num_buffer_reads[vnet]++;
  95     }
  96 }
  97
  98 uint32_t
  99 InputUnit_d::functionalWrite(Packet *pkt)
 100 {
 101     uint32_t num_functional_writes = 0;
 102     for (int i=0; i < m_num_vcs; i++) {
 103         num_functional_writes += m_vcs[i]->functionalWrite(pkt);
 104     }
 105
 106     return num_functional_writes;
 107 }
 108
 109 void
 110 InputUnit_d::resetStats()
 111 {
 112     for (int j = 0; j < m_num_buffer_reads.size(); j++) {
 113         m_num_buffer_reads[j] = 0;
 114         m_num_buffer_writes[j] = 0;
 115     }
 116 }