garnet: added orion2.0 for network power calculation
[gem5.git] / src / mem / ruby / network / orion / Buffer / SRAM.hh
1 /*
2 * Copyright (c) 2009 Princeton University, and
3 * Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Hangsheng Wang (Orion 1.0, Princeton)
30 * Xinping Zhu (Orion 1.0, Princeton)
31 * Xuning Chen (Orion 1.0, Princeton)
32 * Bin Li (Orion 2.0, Princeton)
33 * Kambiz Samadi (Orion 2.0, UC San Diego)
34 */
35
36 #ifndef __SRAM_H__
37 #define __SRAM_H__
38
39 #include "mem/ruby/network/orion/Type.hh"
40 #include "mem/ruby/network/orion/OrionConfig.hh"
41 #include "mem/ruby/network/orion/TechParameter.hh"
42
43 class OutdrvUnit;
44 class AmpUnit;
45 class BitlineUnit;
46 class MemUnit;
47 class PrechargeUnit;
48 class WordlineUnit;
49 class DecoderUnit;
50
51 class SRAM
52 {
53 public:
54 SRAM(
55 uint32_t num_entry_,
56 uint32_t line_width_,
57 bool is_fifo_,
58 bool is_outdrv_,
59 uint32_t num_read_port_,
60 uint32_t num_write_port_,
61 uint32_t num_data_end_,
62 const string& rowdec_model_str_,
63 const string& wl_model_str_,
64 const string& bl_pre_model_str_,
65 const string& mem_model_str_,
66 const string& bl_model_str_,
67 const string& amp_model_str_,
68 const string& outdrv_model_str_,
69 const TechParameter* tech_param_ptr_
70 );
71 ~SRAM();
72
73 public:
74 uint32_t get_line_width() const { return m_line_width; }
75 uint32_t get_num_data_end() const { return m_num_data_end; }
76 uint32_t get_num_read_port() const { return m_num_read_port; }
77 uint32_t get_num_write_port() const { return m_num_write_port; }
78 uint32_t get_num_port() const { return (m_num_read_port+m_num_write_port); }
79 bool get_is_outdrv() const { return m_is_outdrv; }
80 uint32_t get_num_row() const { return m_num_entry; }
81 uint32_t get_num_col() const { return m_line_width; }
82
83 double calc_e_read(bool is_max_) const;
84 double calc_e_write(bool is_max_) const;
85 double calc_i_static() const;
86
87 private:
88 void init();
89
90 private:
91 uint32_t m_num_entry;
92 uint32_t m_line_width;
93 bool m_is_fifo;
94 bool m_is_outdrv;
95 string m_rowdec_model_str;
96 string m_wl_model_str;
97 string m_bl_pre_model_str;
98 string m_mem_model_str;
99 string m_bl_model_str;
100 string m_amp_model_str;
101 string m_outdrv_model_str;
102 const TechParameter* m_tech_param_ptr;
103
104 OutdrvUnit* m_outdrv_unit_ptr;
105 AmpUnit* m_amp_unit_ptr;
106 BitlineUnit* m_bl_unit_ptr;
107 MemUnit* m_mem_unit_ptr;
108 PrechargeUnit* m_bl_pre_unit_ptr;
109 WordlineUnit* m_wl_unit_ptr;
110 DecoderUnit* m_rowdec_unit_ptr;
111
112 uint32_t m_num_read_port;
113 uint32_t m_num_write_port;
114 uint32_t m_num_data_end;
115
116 uint32_t m_rowdec_width;
117 };
118
119 #endif
120