src/mem/ruby/profiler/Profiler.hh

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30    This file has been modified by Kevin Moore and Dan Nussbaum of the
  31    Scalable Systems Research Group at Sun Microsystems Laboratories
  32    (http://research.sun.com/scalable/) to support the Adaptive
  33    Transactional Memory Test Platform (ATMTP).
  34
  35    Please send email to atmtp-interest@sun.com with feedback, questions, or
  36    to request future announcements about ATMTP.
  37
  38    ----------------------------------------------------------------------
  39
  40    File modification date: 2008-02-23
  41
  42    ----------------------------------------------------------------------
  43 */
  44
  45 #ifndef __MEM_RUBY_PROFILER_PROFILER_HH__
  46 #define __MEM_RUBY_PROFILER_PROFILER_HH__
  47
  48 #include <map>
  49 #include <memory>
  50 #include <string>
  51 #include <vector>
  52
  53 #include "base/callback.hh"
  54 #include "base/statistics.hh"
  55 #include "mem/ruby/common/MachineID.hh"
  56 #include "mem/ruby/protocol/AccessType.hh"
  57 #include "mem/ruby/protocol/PrefetchBit.hh"
  58 #include "mem/ruby/protocol/RubyAccessMode.hh"
  59 #include "mem/ruby/protocol/RubyRequestType.hh"
  60 #include "params/RubySystem.hh"
  61
  62 class RubyRequest;
  63 class AddressProfiler;
  64
  65 class Profiler
  66 {
  67   public:
  68     Profiler(const RubySystemParams &params, RubySystem *rs);
  69     ~Profiler();
  70
  71     RubySystem *m_ruby_system;
  72
  73     void wakeup();
  74     void regStats();
  75     void collateStats();
  76
  77     AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; }
  78     AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; }
  79
  80     void addAddressTraceSample(const RubyRequest& msg, NodeID id);
  81
  82     // added by SS
  83     bool getHotLines() const { return m_hot_lines; }
  84     bool getAllInstructions() const { return m_all_instructions; }
  85
  86   private:
  87     // Private copy constructor and assignment operator
  88     Profiler(const Profiler& obj);
  89     Profiler& operator=(const Profiler& obj);
  90
  91     AddressProfiler* m_address_profiler_ptr;
  92     AddressProfiler* m_inst_profiler_ptr;
  93
  94     struct ProfilerStats : public Stats::Group
  95     {
  96         ProfilerStats(Stats::Group *parent, Profiler *profiler);
  97
  98         struct PerRequestTypeStats : public Stats::Group
  99         {
 100             PerRequestTypeStats(Stats::Group *parent);
 101
 102             // Histogram of the latency of each request type
 103             std::vector<Stats::Histogram *> m_typeLatencyHistSeqr;
 104             std::vector<Stats::Histogram *> m_typeLatencyHistCoalsr;
 105
 106             // Histogram of the latency of requests that hit in the controller
 107             // connected to this sequencer for each type of request
 108             std::vector<Stats::Histogram *> m_hitTypeLatencyHistSeqr;
 109
 110             // Histogram of the latency of requests that miss in the controller
 111             // connected to this sequencer for each type of request
 112             std::vector<Stats::Histogram *> m_missTypeLatencyHistSeqr;
 113             std::vector<Stats::Histogram *> m_missTypeLatencyHistCoalsr;
 114         } perRequestTypeStats;
 115
 116         struct PerMachineTypeStats : public Stats::Group
 117         {
 118             PerMachineTypeStats(Stats::Group *parent);
 119
 120             //! Histograms for profiling the latencies for requests that
 121             //! did not required external messages.
 122             std::vector<Stats::Histogram *> m_hitMachLatencyHistSeqr;
 123
 124             //! Histograms for profiling the latencies for requests that
 125             //! required external messages.
 126             std::vector<Stats::Histogram *> m_missMachLatencyHistSeqr;
 127             std::vector<Stats::Histogram *> m_missMachLatencyHistCoalsr;
 128
 129             //! Histograms for recording the breakdown of miss latency
 130             std::vector<Stats::Histogram *> m_IssueToInitialDelayHistSeqr;
 131             std::vector<Stats::Histogram *> m_InitialToForwardDelayHistSeqr;
 132             std::vector<Stats::Histogram *>
 133               m_ForwardToFirstResponseDelayHistSeqr;
 134             std::vector<Stats::Histogram *>
 135               m_FirstResponseToCompletionDelayHistSeqr;
 136             std::vector<Stats::Scalar *> m_IncompleteTimesSeqr;
 137             std::vector<Stats::Histogram *> m_IssueToInitialDelayHistCoalsr;
 138             std::vector<Stats::Histogram *> m_InitialToForwardDelayHistCoalsr;
 139             std::vector<Stats::Histogram *>
 140               m_ForwardToFirstResponseDelayHistCoalsr;
 141             std::vector<Stats::Histogram *>
 142               m_FirstResponseToCompletionDelayHistCoalsr;
 143         } perMachineTypeStats;
 144
 145         struct PerRequestTypeMachineTypeStats : public Stats::Group
 146         {
 147             PerRequestTypeMachineTypeStats(Stats::Group *parent);
 148
 149             //! Histograms for profiling the latencies for requests that
 150             //! did not required external messages.
 151             std::vector< std::vector<Stats::Histogram *> >
 152               m_hitTypeMachLatencyHistSeqr;
 153
 154             //! Histograms for profiling the latencies for requests that
 155             //! required external messages.
 156             std::vector< std::vector<Stats::Histogram *> >
 157               m_missTypeMachLatencyHistSeqr;
 158             std::vector< std::vector<Stats::Histogram *> >
 159               m_missTypeMachLatencyHistCoalsr;
 160         } perRequestTypeMachineTypeStats;
 161
 162         Stats::Histogram delayHistogram;
 163         std::vector<Stats::Histogram *> delayVCHistogram;
 164
 165         //! Histogram for number of outstanding requests per cycle.
 166         Stats::Histogram m_outstandReqHistSeqr;
 167         Stats::Histogram m_outstandReqHistCoalsr;
 168
 169         //! Histogram for holding latency profile of all requests.
 170         Stats::Histogram m_latencyHistSeqr;
 171         Stats::Histogram m_latencyHistCoalsr;
 172
 173         //! Histogram for holding latency profile of all requests that
 174         //! hit in the controller connected to this sequencer.
 175         Stats::Histogram m_hitLatencyHistSeqr;
 176
 177         //! Histogram for holding latency profile of all requests that
 178         //! miss in the controller connected to this sequencer.
 179         Stats::Histogram m_missLatencyHistSeqr;
 180         Stats::Histogram m_missLatencyHistCoalsr;
 181     };
 182
 183     //added by SS
 184     const bool m_hot_lines;
 185     const bool m_all_instructions;
 186     const uint32_t m_num_vnets;
 187
 188     ProfilerStats rubyProfilerStats;
 189 };
 190
 191 #endif // __MEM_RUBY_PROFILER_PROFILER_HH__