src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm

   1 /*
   2  * Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 machine(MachineType:CorePair, "CP-like Core Coherence")
  35  : Sequencer * sequencer;
  36    Sequencer * sequencer1;
  37    CacheMemory * L1Icache;
  38    CacheMemory * L1D0cache;
  39    CacheMemory * L1D1cache;
  40    CacheMemory * L2cache;     // func mem logic looks in this CacheMemory
  41    bool send_evictions := "False";
  42    Cycles issue_latency := 5;  // time to send data down to NB
  43    Cycles l2_hit_latency := 18;
  44
  45   // BEGIN Core Buffers
  46
  47   // To the Network
  48   MessageBuffer * requestFromCore, network="To", virtual_network="0", vnet_type="request";
  49   MessageBuffer * responseFromCore, network="To", virtual_network="2", vnet_type="response";
  50   MessageBuffer * unblockFromCore, network="To", virtual_network="4", vnet_type="unblock";
  51
  52   // From the Network
  53   MessageBuffer * probeToCore, network="From", virtual_network="0", vnet_type="request";
  54   MessageBuffer * responseToCore, network="From", virtual_network="2", vnet_type="response";
  55
  56   MessageBuffer * mandatoryQueue;
  57
  58   MessageBuffer * triggerQueue, ordered="true";
  59
  60   // END Core Buffers
  61
  62 {
  63   // BEGIN STATES
  64   state_declaration(State, desc="Cache states", default="CorePair_State_I") {
  65
  66     // Base States
  67     I, AccessPermission:Invalid, desc="Invalid";
  68     S, AccessPermission:Read_Only, desc="Shared";
  69     E0, AccessPermission:Read_Write, desc="Exclusive with Cluster 0 ownership";
  70     E1, AccessPermission:Read_Write, desc="Exclusive with Cluster 1 ownership";
  71     Es, AccessPermission:Read_Write, desc="Exclusive in core";
  72     O, AccessPermission:Read_Only, desc="Owner state in core, both clusters and other cores may be sharing line";
  73     Ms, AccessPermission:Read_Write, desc="Modified in core, both clusters may be sharing line";
  74     M0, AccessPermission:Read_Write, desc="Modified with cluster ownership";
  75     M1, AccessPermission:Read_Write, desc="Modified with cluster ownership";
  76
  77     // Transient States
  78     I_M0, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
  79     I_M1, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
  80     I_M0M1, AccessPermission:Busy, desc="Was in I_M0, got a store request from other cluster as well";
  81     I_M1M0, AccessPermission:Busy, desc="Was in I_M1, got a store request from other cluster as well";
  82     I_M0Ms, AccessPermission:Busy, desc="Was in I_M0, got a load request from other cluster as well";
  83     I_M1Ms, AccessPermission:Busy, desc="Was in I_M1, got a load request from other cluster as well";
  84     I_E0S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
  85     I_E1S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
  86     I_ES, AccessPermission:Busy, desc="S_F got hit by invalidating probe, RdBlk response needs to go to both clusters";
  87
  88     IF_E0S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E0S but expecting a L2_to_L1D0 trigger, just drop when receive";
  89     IF_E1S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E1S but expecting a L2_to_L1D1 trigger, just drop when receive";
  90     IF_ES, AccessPermission:Busy, desc="same, but waiting for two fills";
  91     IF0_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
  92     IF1_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
  93     F_S0, AccessPermission:Busy, desc="same, but going to S0 when trigger received";
  94     F_S1, AccessPermission:Busy, desc="same, but going to S1 when trigger received";
  95
  96     ES_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for clean writeback ack";
  97     MO_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for dirty writeback ack";
  98     MO_S0, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
  99     MO_S1, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
 100     S_F0, AccessPermission:Read_Only,  desc="Shared, filling L1";
 101     S_F1, AccessPermission:Read_Only,  desc="Shared, filling L1";
 102     S_F, AccessPermission:Read_Only,   desc="Shared, filling L1";
 103     O_F0, AccessPermission:Read_Only,  desc="Owned, filling L1";
 104     O_F1, AccessPermission:Read_Only,  desc="Owned, filling L1";
 105     O_F,  AccessPermission:Read_Only,  desc="Owned, filling L1";
 106     Si_F0, AccessPermission:Read_Only, desc="Shared, filling icache";
 107     Si_F1, AccessPermission:Read_Only, desc="Shared, filling icache";
 108     S_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 109     S_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 110     O_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 111     O_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 112     S0, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 0, waiting for response";
 113     S1, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 1, waiting for response";
 114
 115     Es_F0, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
 116     Es_F1, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
 117     Es_F, AccessPermission:Read_Write,  desc="Es, other cluster read, filling";
 118     E0_F, AccessPermission:Read_Write, desc="E0, cluster read, filling";
 119     E1_F, AccessPermission:Read_Write, desc="...";
 120     E0_Es, AccessPermission:Read_Write, desc="...";
 121     E1_Es, AccessPermission:Read_Write, desc="...";
 122     Ms_F0, AccessPermission:Read_Write, desc="...";
 123     Ms_F1, AccessPermission:Read_Write, desc="...";
 124     Ms_F, AccessPermission:Read_Write,  desc="...";
 125     M0_F, AccessPermission:Read_Write, desc="...";
 126     M0_Ms, AccessPermission:Read_Write, desc="...";
 127     M1_F, AccessPermission:Read_Write, desc="...";
 128     M1_Ms, AccessPermission:Read_Write, desc="...";
 129
 130     I_C, AccessPermission:Invalid, desc="Invalid, but waiting for WBAck from NB from canceled writeback";
 131     S0_C, AccessPermission:Busy, desc="MO_S0 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
 132     S1_C, AccessPermission:Busy, desc="MO_S1 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
 133     S_C, AccessPermission:Busy, desc="S*_C got NB_AckS, still waiting for WBAck";
 134
 135   } // END STATES
 136
 137   // BEGIN EVENTS
 138   enumeration(Event, desc="CP Events") {
 139     // CP Initiated events
 140     C0_Load_L1miss,            desc="Cluster 0 load, L1 missed";
 141     C0_Load_L1hit,             desc="Cluster 0 load, L1 hit";
 142     C1_Load_L1miss,            desc="Cluster 1 load L1 missed";
 143     C1_Load_L1hit,             desc="Cluster 1 load L1 hit";
 144     Ifetch0_L1hit,             desc="Instruction fetch, hit in the L1";
 145     Ifetch1_L1hit,             desc="Instruction fetch, hit in the L1";
 146     Ifetch0_L1miss,            desc="Instruction fetch, missed in the L1";
 147     Ifetch1_L1miss,            desc="Instruction fetch, missed in the L1";
 148     C0_Store_L1miss,           desc="Cluster 0 store missed in L1";
 149     C0_Store_L1hit,            desc="Cluster 0 store hit in L1";
 150     C1_Store_L1miss,           desc="Cluster 1 store missed in L1";
 151     C1_Store_L1hit,            desc="Cluster 1 store hit in L1";
 152     // NB Initiated events
 153     NB_AckS,             desc="NB Ack to Core Request";
 154     NB_AckM,             desc="NB Ack to Core Request";
 155     NB_AckE,             desc="NB Ack to Core Request";
 156
 157     NB_AckWB,            desc="NB Ack for writeback";
 158
 159     // Memory System initiatied events
 160     L1I_Repl,           desc="Replace address from L1I"; // Presumed clean
 161     L1D0_Repl,           desc="Replace address from L1D0"; // Presumed clean
 162     L1D1_Repl,           desc="Replace address from L1D1"; // Presumed clean
 163     L2_Repl,            desc="Replace address from L2";
 164
 165     L2_to_L1D0,           desc="L1 fill from L2";
 166     L2_to_L1D1,           desc="L1 fill from L2";
 167     L2_to_L1I,           desc="L1 fill from L2";
 168
 169     // Probe Events
 170     PrbInvData,         desc="probe, return O or M data";
 171     PrbInv,             desc="probe, no need for data";
 172     PrbShrData,         desc="probe downgrade, return O or M data";
 173
 174   }  // END EVENTS
 175
 176   enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
 177     L1D0DataArrayRead,    desc="Read the data array";
 178     L1D0DataArrayWrite,   desc="Write the data array";
 179     L1D0TagArrayRead,     desc="Read the data array";
 180     L1D0TagArrayWrite,    desc="Write the data array";
 181     L1D1DataArrayRead,    desc="Read the data array";
 182     L1D1DataArrayWrite,   desc="Write the data array";
 183     L1D1TagArrayRead,     desc="Read the data array";
 184     L1D1TagArrayWrite,    desc="Write the data array";
 185     L1IDataArrayRead,     desc="Read the data array";
 186     L1IDataArrayWrite,    desc="Write the data array";
 187     L1ITagArrayRead,      desc="Read the data array";
 188     L1ITagArrayWrite,     desc="Write the data array";
 189     L2DataArrayRead,      desc="Read the data array";
 190     L2DataArrayWrite,     desc="Write the data array";
 191     L2TagArrayRead,       desc="Read the data array";
 192     L2TagArrayWrite,      desc="Write the data array";
 193   }
 194
 195
 196   // BEGIN STRUCTURE DEFINITIONS
 197
 198
 199   // Cache Entry
 200   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 201     State CacheState,           desc="cache state";
 202     bool Dirty,                 desc="Is the data dirty (diff than memory)?";
 203     DataBlock DataBlk,          desc="data for the block";
 204     bool FromL2, default="false", desc="block just moved from L2";
 205   }
 206
 207   structure(TBE, desc="...") {
 208     State TBEState,             desc="Transient state";
 209     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 210     bool Dirty,              desc="Is the data dirty (different than memory)?";
 211     int NumPendingMsgs,      desc="Number of acks/data messages that this processor is waiting for";
 212     bool Shared,             desc="Victim hit by shared probe";
 213    }
 214
 215   structure(TBETable, external="yes") {
 216     TBE lookup(Addr);
 217     void allocate(Addr);
 218     void deallocate(Addr);
 219     bool isPresent(Addr);
 220   }
 221
 222   TBETable TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
 223
 224   void set_cache_entry(AbstractCacheEntry b);
 225   void unset_cache_entry();
 226   void set_tbe(TBE b);
 227   void unset_tbe();
 228   void wakeUpAllBuffers();
 229   void wakeUpBuffers(Addr a);
 230   Cycles curCycle();
 231   MachineID mapAddressToMachine(Addr addr, MachineType mtype);
 232
 233   // END STRUCTURE DEFINITIONS
 234
 235   // BEGIN INTERNAL FUNCTIONS
 236
 237   Tick clockEdge();
 238   Tick cyclesToTicks(Cycles c);
 239
 240   bool addressInCore(Addr addr) {
 241     return (L2cache.isTagPresent(addr) || L1Icache.isTagPresent(addr) || L1D0cache.isTagPresent(addr) || L1D1cache.isTagPresent(addr));
 242   }
 243
 244   Entry getCacheEntry(Addr address), return_by_pointer="yes" {
 245     Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
 246     return L2cache_entry;
 247   }
 248
 249   DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
 250     TBE tbe := TBEs.lookup(addr);
 251     if(is_valid(tbe)) {
 252       return tbe.DataBlk;
 253     } else {
 254       return getCacheEntry(addr).DataBlk;
 255     }
 256   }
 257
 258   Entry getL1CacheEntry(Addr addr, int cluster), return_by_pointer="yes" {
 259     if (cluster == 0) {
 260       Entry L1D0_entry := static_cast(Entry, "pointer", L1D0cache.lookup(addr));
 261       return L1D0_entry;
 262     } else {
 263       Entry L1D1_entry := static_cast(Entry, "pointer", L1D1cache.lookup(addr));
 264       return L1D1_entry;
 265     }
 266   }
 267
 268   Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
 269     Entry c_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
 270     return c_entry;
 271   }
 272
 273   bool presentOrAvail2(Addr addr) {
 274     return L2cache.isTagPresent(addr) || L2cache.cacheAvail(addr);
 275   }
 276
 277   bool presentOrAvailI(Addr addr) {
 278     return L1Icache.isTagPresent(addr) || L1Icache.cacheAvail(addr);
 279   }
 280
 281   bool presentOrAvailD0(Addr addr) {
 282     return L1D0cache.isTagPresent(addr) || L1D0cache.cacheAvail(addr);
 283   }
 284
 285   bool presentOrAvailD1(Addr addr) {
 286     return L1D1cache.isTagPresent(addr) || L1D1cache.cacheAvail(addr);
 287   }
 288
 289   State getState(TBE tbe, Entry cache_entry, Addr addr) {
 290     if(is_valid(tbe)) {
 291       return tbe.TBEState;
 292     } else if (is_valid(cache_entry)) {
 293       return cache_entry.CacheState;
 294     }
 295     return State:I;
 296   }
 297
 298   void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
 299     if (is_valid(tbe)) {
 300       tbe.TBEState := state;
 301     }
 302
 303     if (is_valid(cache_entry)) {
 304       cache_entry.CacheState := state;
 305     }
 306   }
 307
 308   AccessPermission getAccessPermission(Addr addr) {
 309     TBE tbe := TBEs.lookup(addr);
 310     if(is_valid(tbe)) {
 311       return CorePair_State_to_permission(tbe.TBEState);
 312     }
 313
 314     Entry cache_entry := getCacheEntry(addr);
 315     if(is_valid(cache_entry)) {
 316       return CorePair_State_to_permission(cache_entry.CacheState);
 317     }
 318
 319     return AccessPermission:NotPresent;
 320   }
 321
 322   void functionalRead(Addr addr, Packet *pkt) {
 323     TBE tbe := TBEs.lookup(addr);
 324     if(is_valid(tbe)) {
 325       testAndRead(addr, tbe.DataBlk, pkt);
 326     } else {
 327       functionalMemoryRead(pkt);
 328     }
 329   }
 330
 331   int functionalWrite(Addr addr, Packet *pkt) {
 332     int num_functional_writes := 0;
 333
 334     TBE tbe := TBEs.lookup(addr);
 335     if(is_valid(tbe)) {
 336       num_functional_writes := num_functional_writes +
 337             testAndWrite(addr, tbe.DataBlk, pkt);
 338     }
 339
 340     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
 341     return num_functional_writes;
 342   }
 343
 344   void setAccessPermission(Entry cache_entry, Addr addr, State state) {
 345     if (is_valid(cache_entry)) {
 346       cache_entry.changePermission(CorePair_State_to_permission(state));
 347     }
 348   }
 349
 350   MachineType testAndClearLocalHit(Entry cache_entry) {
 351     assert(is_valid(cache_entry));
 352     if (cache_entry.FromL2) {
 353       cache_entry.FromL2 := false;
 354       return MachineType:L2Cache;
 355     } else {
 356       return MachineType:L1Cache;
 357     }
 358   }
 359
 360   void recordRequestType(RequestType request_type, Addr addr) {
 361     if (request_type == RequestType:L1D0DataArrayRead) {
 362         L1D0cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 363     } else if (request_type == RequestType:L1D0DataArrayWrite) {
 364         L1D0cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 365     } else if (request_type == RequestType:L1D0TagArrayRead) {
 366         L1D0cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 367     } else if (request_type == RequestType:L1D0TagArrayWrite) {
 368         L1D0cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 369     } else if (request_type == RequestType:L1D1DataArrayRead) {
 370         L1D1cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 371     } else if (request_type == RequestType:L1D1DataArrayWrite) {
 372         L1D1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 373     } else if (request_type == RequestType:L1D1TagArrayRead) {
 374         L1D1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 375     } else if (request_type == RequestType:L1D1TagArrayWrite) {
 376         L1D1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 377     } else if (request_type == RequestType:L1IDataArrayRead) {
 378         L1Icache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 379     } else if (request_type == RequestType:L1IDataArrayWrite) {
 380         L1Icache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 381     } else if (request_type == RequestType:L1ITagArrayRead) {
 382         L1Icache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 383     } else if (request_type == RequestType:L1ITagArrayWrite) {
 384         L1Icache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 385     } else if (request_type == RequestType:L2DataArrayRead) {
 386         L2cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 387     } else if (request_type == RequestType:L2DataArrayWrite) {
 388         L2cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 389     } else if (request_type == RequestType:L2TagArrayRead) {
 390         L2cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 391     } else if (request_type == RequestType:L2TagArrayWrite) {
 392         L2cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 393     }
 394   }
 395
 396   bool checkResourceAvailable(RequestType request_type, Addr addr) {
 397     if (request_type == RequestType:L2DataArrayRead) {
 398       return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 399     } else if (request_type == RequestType:L2DataArrayWrite) {
 400       return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 401     } else if (request_type == RequestType:L2TagArrayRead) {
 402       return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 403     } else if (request_type == RequestType:L2TagArrayWrite) {
 404       return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 405     } else if  (request_type == RequestType:L1D0DataArrayRead) {
 406       return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 407     } else if (request_type == RequestType:L1D0DataArrayWrite) {
 408       return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 409     } else if (request_type == RequestType:L1D0TagArrayRead) {
 410       return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 411     } else if (request_type == RequestType:L1D0TagArrayWrite) {
 412       return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 413     } else if (request_type == RequestType:L1D1DataArrayRead) {
 414       return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 415     } else if (request_type == RequestType:L1D1DataArrayWrite) {
 416       return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 417     } else if (request_type == RequestType:L1D1TagArrayRead) {
 418       return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 419     } else if (request_type == RequestType:L1D1TagArrayWrite) {
 420       return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 421     } else if (request_type == RequestType:L1IDataArrayRead) {
 422       return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 423     } else if (request_type == RequestType:L1IDataArrayWrite) {
 424       return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 425     } else if (request_type == RequestType:L1ITagArrayRead) {
 426       return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 427     } else if (request_type == RequestType:L1ITagArrayWrite) {
 428       return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 429
 430     } else {
 431       return true;
 432     }
 433   }
 434
 435   // END INTERNAL FUNCTIONS
 436
 437   // ** OUT_PORTS **
 438
 439   out_port(requestNetwork_out, CPURequestMsg, requestFromCore);
 440   out_port(responseNetwork_out, ResponseMsg, responseFromCore);
 441   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 442   out_port(unblockNetwork_out, UnblockMsg, unblockFromCore);
 443
 444   // ** IN_PORTS **
 445
 446   in_port(triggerQueue_in, TriggerMsg, triggerQueue, block_on="addr") {
 447     if (triggerQueue_in.isReady(clockEdge())) {
 448       peek(triggerQueue_in, TriggerMsg) {
 449         Entry cache_entry := getCacheEntry(in_msg.addr);
 450         TBE tbe := TBEs.lookup(in_msg.addr);
 451
 452         if (in_msg.Type == TriggerType:L2_to_L1) {
 453           if (in_msg.Dest == CacheId:L1I) {
 454             trigger(Event:L2_to_L1I, in_msg.addr, cache_entry, tbe);
 455           } else if (in_msg.Dest == CacheId:L1D0) {
 456             trigger(Event:L2_to_L1D0, in_msg.addr, cache_entry, tbe);
 457           } else if (in_msg.Dest == CacheId:L1D1) {
 458             trigger(Event:L2_to_L1D1, in_msg.addr, cache_entry, tbe);
 459           } else {
 460             error("unexpected trigger dest");
 461           }
 462         }
 463       }
 464     }
 465   }
 466
 467
 468   in_port(probeNetwork_in, NBProbeRequestMsg, probeToCore) {
 469     if (probeNetwork_in.isReady(clockEdge())) {
 470       peek(probeNetwork_in, NBProbeRequestMsg, block_on="addr") {
 471         Entry cache_entry := getCacheEntry(in_msg.addr);
 472         TBE tbe := TBEs.lookup(in_msg.addr);
 473
 474         if (in_msg.Type == ProbeRequestType:PrbInv) {
 475           if (in_msg.ReturnData) {
 476             trigger(Event:PrbInvData, in_msg.addr, cache_entry, tbe);
 477           } else {
 478             trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe);
 479           }
 480         } else if (in_msg.Type == ProbeRequestType:PrbDowngrade) {
 481           assert(in_msg.ReturnData);
 482           trigger(Event:PrbShrData, in_msg.addr, cache_entry, tbe);
 483         }
 484       }
 485     }
 486   }
 487
 488
 489   // ResponseNetwork
 490   in_port(responseToCore_in, ResponseMsg, responseToCore) {
 491     if (responseToCore_in.isReady(clockEdge())) {
 492       peek(responseToCore_in, ResponseMsg, block_on="addr") {
 493
 494         Entry cache_entry := getCacheEntry(in_msg.addr);
 495         TBE tbe := TBEs.lookup(in_msg.addr);
 496
 497         if (in_msg.Type == CoherenceResponseType:NBSysResp) {
 498           if (in_msg.State == CoherenceState:Modified) {
 499               trigger(Event:NB_AckM, in_msg.addr, cache_entry, tbe);
 500           } else if (in_msg.State == CoherenceState:Shared) {
 501             trigger(Event:NB_AckS, in_msg.addr, cache_entry, tbe);
 502           } else if (in_msg.State == CoherenceState:Exclusive) {
 503             trigger(Event:NB_AckE, in_msg.addr, cache_entry, tbe);
 504           }
 505         } else if (in_msg.Type == CoherenceResponseType:NBSysWBAck) {
 506           trigger(Event:NB_AckWB, in_msg.addr, cache_entry, tbe);
 507         } else {
 508           error("Unexpected Response Message to Core");
 509         }
 510       }
 511     }
 512   }
 513
 514   // Nothing from the Unblock Network
 515
 516   // Mandatory Queue
 517   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
 518     if (mandatoryQueue_in.isReady(clockEdge())) {
 519       peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
 520
 521         Entry cache_entry := getCacheEntry(in_msg.LineAddress);
 522         TBE tbe := TBEs.lookup(in_msg.LineAddress);
 523
 524         if (in_msg.Type == RubyRequestType:IFETCH) {
 525           // FETCH ACCESS
 526
 527           if (L1Icache.isTagPresent(in_msg.LineAddress)) {
 528             if (mod(in_msg.contextId, 2) == 0) {
 529               trigger(Event:Ifetch0_L1hit, in_msg.LineAddress, cache_entry, tbe);
 530             } else {
 531               trigger(Event:Ifetch1_L1hit, in_msg.LineAddress, cache_entry, tbe);
 532             }
 533           } else {
 534             if (presentOrAvail2(in_msg.LineAddress)) {
 535               if (presentOrAvailI(in_msg.LineAddress)) {
 536                 if (mod(in_msg.contextId, 2) == 0) {
 537                   trigger(Event:Ifetch0_L1miss, in_msg.LineAddress, cache_entry,
 538                           tbe);
 539                 } else {
 540                   trigger(Event:Ifetch1_L1miss, in_msg.LineAddress, cache_entry,
 541                           tbe);
 542                 }
 543               } else {
 544                 // Check if the line we want to evict is not locked
 545                 Addr victim := L1Icache.cacheProbe(in_msg.LineAddress);
 546                 check_on_cache_probe(mandatoryQueue_in, victim);
 547                 trigger(Event:L1I_Repl, victim,
 548                         getCacheEntry(victim), TBEs.lookup(victim));
 549               }
 550             } else { // Not present or avail in L2
 551               Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 552               trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 553                       TBEs.lookup(victim));
 554             }
 555           }
 556         } else {
 557           // DATA ACCESS
 558           if (mod(in_msg.contextId, 2) == 1) {
 559             if (L1D1cache.isTagPresent(in_msg.LineAddress)) {
 560               if (in_msg.Type == RubyRequestType:LD) {
 561                 trigger(Event:C1_Load_L1hit, in_msg.LineAddress, cache_entry,
 562                         tbe);
 563               } else {
 564                 // Stores must write through, make sure L2 avail.
 565                 if (presentOrAvail2(in_msg.LineAddress)) {
 566                   trigger(Event:C1_Store_L1hit, in_msg.LineAddress, cache_entry,
 567                           tbe);
 568                 } else {
 569                   Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 570                   trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 571                           TBEs.lookup(victim));
 572                 }
 573               }
 574             } else {
 575               if (presentOrAvail2(in_msg.LineAddress)) {
 576                 if (presentOrAvailD1(in_msg.LineAddress)) {
 577                   if (in_msg.Type == RubyRequestType:LD) {
 578                     trigger(Event:C1_Load_L1miss, in_msg.LineAddress,
 579                             cache_entry, tbe);
 580                   } else {
 581                     trigger(Event:C1_Store_L1miss, in_msg.LineAddress,
 582                             cache_entry, tbe);
 583                   }
 584                 } else {
 585                   // Check if the line we want to evict is not locked
 586                   Addr victim := L1D1cache.cacheProbe(in_msg.LineAddress);
 587                   check_on_cache_probe(mandatoryQueue_in, victim);
 588                   trigger(Event:L1D1_Repl, victim,
 589                           getCacheEntry(victim), TBEs.lookup(victim));
 590                 }
 591               } else { // not present or avail in L2
 592                 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 593                 trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
 594               }
 595             }
 596           } else {
 597             Entry L1D0cache_entry := getL1CacheEntry(in_msg.LineAddress, 0);
 598             if (is_valid(L1D0cache_entry)) {
 599               if (in_msg.Type == RubyRequestType:LD) {
 600                 trigger(Event:C0_Load_L1hit, in_msg.LineAddress, cache_entry,
 601                     tbe);
 602               } else {
 603                 if (presentOrAvail2(in_msg.LineAddress)) {
 604                   trigger(Event:C0_Store_L1hit, in_msg.LineAddress, cache_entry,
 605                       tbe);
 606                 } else {
 607                   Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 608                   trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 609                       TBEs.lookup(victim));
 610                 }
 611               }
 612             } else {
 613               if (presentOrAvail2(in_msg.LineAddress)) {
 614                 if (presentOrAvailD0(in_msg.LineAddress)) {
 615                   if (in_msg.Type == RubyRequestType:LD) {
 616                     trigger(Event:C0_Load_L1miss, in_msg.LineAddress,
 617                         cache_entry, tbe);
 618                   } else {
 619                     trigger(Event:C0_Store_L1miss, in_msg.LineAddress,
 620                             cache_entry, tbe);
 621                   }
 622                 } else {
 623                   // Check if the line we want to evict is not locked
 624                   Addr victim := L1D0cache.cacheProbe(in_msg.LineAddress);
 625                   check_on_cache_probe(mandatoryQueue_in, victim);
 626                   trigger(Event:L1D0_Repl, victim, getCacheEntry(victim),
 627                           TBEs.lookup(victim));
 628                 }
 629               } else {
 630                 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 631                 trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 632                         TBEs.lookup(victim));
 633               }
 634             }
 635           }
 636         }
 637       }
 638     }
 639   }
 640
 641
 642   // ACTIONS
 643   action(ii_invIcache, "ii", desc="invalidate iCache") {
 644     if (L1Icache.isTagPresent(address)) {
 645       L1Icache.deallocate(address);
 646     }
 647   }
 648
 649   action(i0_invCluster, "i0", desc="invalidate cluster 0") {
 650     if (L1D0cache.isTagPresent(address)) {
 651       L1D0cache.deallocate(address);
 652     }
 653   }
 654
 655   action(i1_invCluster, "i1", desc="invalidate cluster 1") {
 656     if (L1D1cache.isTagPresent(address)) {
 657       L1D1cache.deallocate(address);
 658     }
 659   }
 660
 661   action(ib_invBothClusters, "ib", desc="invalidate both clusters") {
 662     if (L1D0cache.isTagPresent(address)) {
 663       L1D0cache.deallocate(address);
 664     }
 665     if (L1D1cache.isTagPresent(address)) {
 666       L1D1cache.deallocate(address);
 667     }
 668   }
 669
 670   action(i2_invL2, "i2", desc="invalidate L2") {
 671     if(is_valid(cache_entry)) {
 672         L2cache.deallocate(address);
 673     }
 674     unset_cache_entry();
 675   }
 676
 677   action(mru_setMRU, "mru", desc="Update LRU state") {
 678     L2cache.setMRU(address);
 679   }
 680
 681   action(mruD1_setD1cacheMRU, "mruD1", desc="Update LRU state") {
 682     L1D1cache.setMRU(address);
 683   }
 684
 685   action(mruD0_setD0cacheMRU, "mruD0", desc="Update LRU state") {
 686     L1D0cache.setMRU(address);
 687   }
 688
 689   action(mruI_setIcacheMRU, "mruI", desc="Update LRU state") {
 690     L1Icache.setMRU(address);
 691   }
 692
 693   action(n_issueRdBlk, "n", desc="Issue RdBlk") {
 694     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 695       out_msg.addr := address;
 696       out_msg.Type := CoherenceRequestType:RdBlk;
 697       out_msg.Requestor := machineID;
 698       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 699       DPRINTF(RubySlicc,"%s\n",out_msg.Destination);
 700       out_msg.MessageSize := MessageSizeType:Request_Control;
 701       out_msg.InitialRequestTime := curCycle();
 702     }
 703   }
 704
 705   action(nM_issueRdBlkM, "nM", desc="Issue RdBlkM") {
 706     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 707       out_msg.addr := address;
 708       out_msg.Type := CoherenceRequestType:RdBlkM;
 709       out_msg.Requestor := machineID;
 710       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 711       out_msg.MessageSize := MessageSizeType:Request_Control;
 712       out_msg.InitialRequestTime := curCycle();
 713     }
 714   }
 715
 716   action(nS_issueRdBlkS, "nS", desc="Issue RdBlkS") {
 717     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 718       out_msg.addr := address;
 719       out_msg.Type := CoherenceRequestType:RdBlkS;
 720       out_msg.Requestor := machineID;
 721       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 722       out_msg.MessageSize := MessageSizeType:Request_Control;
 723       out_msg.InitialRequestTime := curCycle();
 724     }
 725   }
 726
 727   action(vd_victim, "vd", desc="Victimize M/O L2 Data") {
 728     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 729       out_msg.addr := address;
 730       out_msg.Requestor := machineID;
 731       assert(is_valid(cache_entry));
 732       out_msg.DataBlk := cache_entry.DataBlk;
 733       assert(cache_entry.Dirty);
 734       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 735       out_msg.MessageSize := MessageSizeType:Request_Control;
 736       out_msg.Type := CoherenceRequestType:VicDirty;
 737       out_msg.InitialRequestTime := curCycle();
 738       if (cache_entry.CacheState == State:O) {
 739         out_msg.Shared := true;
 740       } else {
 741         out_msg.Shared := false;
 742       }
 743     }
 744   }
 745
 746   action(vc_victim, "vc", desc="Victimize E/S L2 Data") {
 747     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 748       out_msg.addr := address;
 749       out_msg.Requestor := machineID;
 750       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 751       out_msg.MessageSize := MessageSizeType:Request_Control;
 752       out_msg.Type := CoherenceRequestType:VicClean;
 753       out_msg.InitialRequestTime := curCycle();
 754       if (cache_entry.CacheState == State:S) {
 755         out_msg.Shared := true;
 756       } else {
 757         out_msg.Shared := false;
 758       }
 759     }
 760   }
 761
 762   action(a0_allocateL1D, "a0", desc="Allocate L1D0 Block") {
 763     if (L1D0cache.isTagPresent(address) == false) {
 764       L1D0cache.allocateVoid(address, new Entry);
 765     }
 766   }
 767
 768   action(a1_allocateL1D, "a1", desc="Allocate L1D1 Block") {
 769     if (L1D1cache.isTagPresent(address) == false) {
 770       L1D1cache.allocateVoid(address, new Entry);
 771     }
 772   }
 773
 774   action(ai_allocateL1I, "ai", desc="Allocate L1I Block") {
 775     if (L1Icache.isTagPresent(address) == false) {
 776       L1Icache.allocateVoid(address, new Entry);
 777     }
 778   }
 779
 780   action(a2_allocateL2, "a2", desc="Allocate L2 Block") {
 781     if (is_invalid(cache_entry)) {
 782       set_cache_entry(L2cache.allocate(address, new Entry));
 783     }
 784   }
 785
 786   action(t_allocateTBE, "t", desc="allocate TBE Entry") {
 787     check_allocate(TBEs);
 788     assert(is_valid(cache_entry));
 789     TBEs.allocate(address);
 790     set_tbe(TBEs.lookup(address));
 791     tbe.DataBlk := cache_entry.DataBlk;  // Data only used for WBs
 792     tbe.Dirty := cache_entry.Dirty;
 793     tbe.Shared := false;
 794   }
 795
 796   action(d_deallocateTBE, "d", desc="Deallocate TBE") {
 797     TBEs.deallocate(address);
 798     unset_tbe();
 799   }
 800
 801   action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") {
 802     mandatoryQueue_in.dequeue(clockEdge());
 803   }
 804
 805   action(pr_popResponseQueue, "pr", desc="Pop Response Queue") {
 806     responseToCore_in.dequeue(clockEdge());
 807   }
 808
 809   action(pt_popTriggerQueue, "pt", desc="Pop Trigger Queue") {
 810     triggerQueue_in.dequeue(clockEdge());
 811   }
 812
 813   action(pp_popProbeQueue, "pp", desc="pop probe queue") {
 814     probeNetwork_in.dequeue(clockEdge());
 815   }
 816
 817   action(il0_loadDone, "il0", desc="Cluster 0 i load done") {
 818     Entry entry := getICacheEntry(address);
 819     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 820     assert(is_valid(entry));
 821     // L2 supplies data (functional accesses only look in L2, ok because L1
 822     //                   writes through to L2)
 823     sequencer.readCallback(address,
 824                            l2entry.DataBlk,
 825                            true,
 826                            testAndClearLocalHit(entry));
 827   }
 828
 829   action(il1_loadDone, "il1", desc="Cluster 1 i load done") {
 830     Entry entry := getICacheEntry(address);
 831     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 832     assert(is_valid(entry));
 833     // L2 supplies data (functional accesses only look in L2, ok because L1
 834     //                   writes through to L2)
 835     sequencer1.readCallback(address,
 836                             l2entry.DataBlk,
 837                             true,
 838                             testAndClearLocalHit(entry));
 839   }
 840
 841   action(l0_loadDone, "l0", desc="Cluster 0 load done") {
 842     Entry entry := getL1CacheEntry(address, 0);
 843     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 844     assert(is_valid(entry));
 845     // L2 supplies data (functional accesses only look in L2, ok because L1
 846     //                   writes through to L2)
 847     sequencer.readCallback(address,
 848                            l2entry.DataBlk,
 849                            true,
 850                            testAndClearLocalHit(entry));
 851   }
 852
 853   action(l1_loadDone, "l1", desc="Cluster 1 load done") {
 854     Entry entry := getL1CacheEntry(address, 1);
 855     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 856     assert(is_valid(entry));
 857     // L2 supplies data (functional accesses only look in L2, ok because L1
 858     //                   writes through to L2)
 859     sequencer1.readCallback(address,
 860                             l2entry.DataBlk,
 861                             true,
 862                             testAndClearLocalHit(entry));
 863   }
 864
 865   action(xl0_loadDone, "xl0", desc="Cluster 0 load done") {
 866     peek(responseToCore_in, ResponseMsg) {
 867       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 868               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 869       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 870       DPRINTF(ProtocolTrace, "CP Load Done 0 -- address %s, data: %s\n", address, l2entry.DataBlk);
 871       // L2 supplies data (functional accesses only look in L2, ok because L1
 872       //                   writes through to L2)
 873       sequencer.readCallback(address,
 874                              l2entry.DataBlk,
 875                              false,
 876                              machineIDToMachineType(in_msg.Sender),
 877                              in_msg.InitialRequestTime,
 878                              in_msg.ForwardRequestTime,
 879                              in_msg.ProbeRequestStartTime);
 880     }
 881   }
 882
 883   action(xl1_loadDone, "xl1", desc="Cluster 1 load done") {
 884    peek(responseToCore_in, ResponseMsg) {
 885       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 886               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 887       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 888       // L2 supplies data (functional accesses only look in L2, ok because L1
 889       //                   writes through to L2)
 890       sequencer1.readCallback(address,
 891                               l2entry.DataBlk,
 892                               false,
 893                               machineIDToMachineType(in_msg.Sender),
 894                               in_msg.InitialRequestTime,
 895                               in_msg.ForwardRequestTime,
 896                               in_msg.ProbeRequestStartTime);
 897     }
 898   }
 899
 900   action(xi0_loadDone, "xi0", desc="Cluster 0 i-load done") {
 901     peek(responseToCore_in, ResponseMsg) {
 902       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 903               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 904       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 905       // L2 supplies data (functional accesses only look in L2, ok because L1
 906       //                   writes through to L2)
 907       sequencer.readCallback(address,
 908                              l2entry.DataBlk,
 909                              false,
 910                              machineIDToMachineType(in_msg.Sender),
 911                              in_msg.InitialRequestTime,
 912                              in_msg.ForwardRequestTime,
 913                              in_msg.ProbeRequestStartTime);
 914     }
 915   }
 916
 917   action(xi1_loadDone, "xi1", desc="Cluster 1 i-load done") {
 918     peek(responseToCore_in, ResponseMsg) {
 919       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 920               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 921       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 922       // L2 supplies data (functional accesses only look in L2, ok because L1
 923       //                   writes through to L2)
 924       sequencer1.readCallback(address,
 925                               l2entry.DataBlk,
 926                               false,
 927                               machineIDToMachineType(in_msg.Sender),
 928                               in_msg.InitialRequestTime,
 929                               in_msg.ForwardRequestTime,
 930                               in_msg.ProbeRequestStartTime);
 931     }
 932   }
 933
 934   action(s0_storeDone, "s0", desc="Cluster 0 store done") {
 935     Entry entry := getL1CacheEntry(address, 0);
 936     assert(is_valid(entry));
 937     assert(is_valid(cache_entry));
 938     sequencer.writeCallback(address,
 939                             cache_entry.DataBlk,
 940                             true,
 941                             testAndClearLocalHit(entry));
 942     cache_entry.Dirty := true;
 943     entry.DataBlk := cache_entry.DataBlk;
 944     entry.Dirty := true;
 945     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 946   }
 947
 948   action(s1_storeDone, "s1", desc="Cluster 1 store done") {
 949     Entry entry := getL1CacheEntry(address, 1);
 950     assert(is_valid(entry));
 951     assert(is_valid(cache_entry));
 952     sequencer1.writeCallback(address,
 953                              cache_entry.DataBlk,
 954                              true,
 955                              testAndClearLocalHit(entry));
 956     cache_entry.Dirty := true;
 957     entry.Dirty := true;
 958     entry.DataBlk := cache_entry.DataBlk;
 959     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 960   }
 961
 962   action(xs0_storeDone, "xs0", desc="Cluster 0 store done") {
 963     peek(responseToCore_in, ResponseMsg) {
 964       Entry entry := getL1CacheEntry(address, 0);
 965       assert(is_valid(entry));
 966       assert(is_valid(cache_entry));
 967       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 968              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 969       sequencer.writeCallback(address,
 970                               cache_entry.DataBlk,
 971                               false,
 972                               machineIDToMachineType(in_msg.Sender),
 973                               in_msg.InitialRequestTime,
 974                               in_msg.ForwardRequestTime,
 975                               in_msg.ProbeRequestStartTime);
 976       cache_entry.Dirty := true;
 977       entry.Dirty := true;
 978       entry.DataBlk := cache_entry.DataBlk;
 979       DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 980     }
 981   }
 982
 983   action(xs1_storeDone, "xs1", desc="Cluster 1 store done") {
 984     peek(responseToCore_in, ResponseMsg) {
 985       Entry entry := getL1CacheEntry(address, 1);
 986       assert(is_valid(entry));
 987       assert(is_valid(cache_entry));
 988       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 989              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 990       sequencer1.writeCallback(address,
 991                                cache_entry.DataBlk,
 992                                false,
 993                                machineIDToMachineType(in_msg.Sender),
 994                                in_msg.InitialRequestTime,
 995                                in_msg.ForwardRequestTime,
 996                                in_msg.ProbeRequestStartTime);
 997       cache_entry.Dirty := true;
 998       entry.Dirty := true;
 999       entry.DataBlk := cache_entry.DataBlk;
1000       DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1001     }
1002   }
1003
1004   action(forward_eviction_to_cpu0, "fec0", desc="sends eviction information to processor0") {
1005     if (send_evictions) {
1006       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1007       sequencer.evictionCallback(address);
1008     }
1009   }
1010
1011   action(forward_eviction_to_cpu1, "fec1", desc="sends eviction information to processor1") {
1012     if (send_evictions) {
1013       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1014       sequencer1.evictionCallback(address);
1015     }
1016   }
1017
1018   action(ci_copyL2ToL1, "ci", desc="copy L2 data to L1") {
1019     Entry entry := getICacheEntry(address);
1020     assert(is_valid(entry));
1021     assert(is_valid(cache_entry));
1022     entry.Dirty := cache_entry.Dirty;
1023     entry.DataBlk := cache_entry.DataBlk;
1024     entry.FromL2 := true;
1025   }
1026
1027   action(c0_copyL2ToL1, "c0", desc="copy L2 data to L1") {
1028     Entry entry := getL1CacheEntry(address, 0);
1029     assert(is_valid(entry));
1030     assert(is_valid(cache_entry));
1031     entry.Dirty := cache_entry.Dirty;
1032     entry.DataBlk := cache_entry.DataBlk;
1033     entry.FromL2 := true;
1034   }
1035
1036   action(c1_copyL2ToL1, "c1", desc="copy L2 data to L1") {
1037     Entry entry := getL1CacheEntry(address, 1);
1038     assert(is_valid(entry));
1039     assert(is_valid(cache_entry));
1040     entry.Dirty := cache_entry.Dirty;
1041     entry.DataBlk := cache_entry.DataBlk;
1042     entry.FromL2 := true;
1043   }
1044
1045   action(fi_L2ToL1, "fi", desc="L2 to L1 inst fill") {
1046     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1047       out_msg.addr := address;
1048       out_msg.Type := TriggerType:L2_to_L1;
1049       out_msg.Dest := CacheId:L1I;
1050     }
1051   }
1052
1053   action(f0_L2ToL1, "f0", desc="L2 to L1 data fill") {
1054     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1055       out_msg.addr := address;
1056       out_msg.Type := TriggerType:L2_to_L1;
1057       out_msg.Dest := CacheId:L1D0;
1058     }
1059   }
1060
1061   action(f1_L2ToL1, "f1", desc="L2 to L1 data fill") {
1062     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1063       out_msg.addr := address;
1064       out_msg.Type := TriggerType:L2_to_L1;
1065       out_msg.Dest := CacheId:L1D1;
1066     }
1067   }
1068
1069   action(wi_writeIcache, "wi", desc="write data to icache (and l2)") {
1070     peek(responseToCore_in, ResponseMsg) {
1071       Entry entry := getICacheEntry(address);
1072       assert(is_valid(entry));
1073       assert(is_valid(cache_entry));
1074       entry.DataBlk := in_msg.DataBlk;
1075       entry.Dirty := in_msg.Dirty;
1076       cache_entry.DataBlk := in_msg.DataBlk;
1077       cache_entry.Dirty := in_msg.Dirty;
1078     }
1079   }
1080
1081   action(w0_writeDcache, "w0", desc="write data to dcache 0 (and l2)") {
1082     peek(responseToCore_in, ResponseMsg) {
1083       Entry entry := getL1CacheEntry(address, 0);
1084       assert(is_valid(entry));
1085       assert(is_valid(cache_entry));
1086       DPRINTF(ProtocolTrace, "CP writeD0: address %s, data: %s\n", address, in_msg.DataBlk);
1087       entry.DataBlk := in_msg.DataBlk;
1088       entry.Dirty := in_msg.Dirty;
1089       cache_entry.DataBlk := in_msg.DataBlk;
1090       cache_entry.Dirty := in_msg.Dirty;
1091     }
1092   }
1093
1094   action(w1_writeDcache, "w1", desc="write data to dcache 1 (and l2)") {
1095     peek(responseToCore_in, ResponseMsg) {
1096       Entry entry := getL1CacheEntry(address, 1);
1097       assert(is_valid(entry));
1098       assert(is_valid(cache_entry));
1099       entry.DataBlk := in_msg.DataBlk;
1100       entry.Dirty := in_msg.Dirty;
1101       cache_entry.DataBlk := in_msg.DataBlk;
1102       cache_entry.Dirty := in_msg.Dirty;
1103     }
1104   }
1105
1106   action(ss_sendStaleNotification, "ss", desc="stale data; nothing to writeback") {
1107     peek(responseToCore_in, ResponseMsg) {
1108       enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1109         out_msg.addr := address;
1110         out_msg.Type := CoherenceResponseType:StaleNotif;
1111         out_msg.Sender := machineID;
1112         out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1113         out_msg.MessageSize := MessageSizeType:Response_Control;
1114         DPRINTF(RubySlicc, "%s\n", out_msg);
1115       }
1116     }
1117   }
1118
1119   action(wb_data, "wb", desc="write back data") {
1120     peek(responseToCore_in, ResponseMsg) {
1121       enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1122         out_msg.addr := address;
1123         out_msg.Type := CoherenceResponseType:CPUData;
1124         out_msg.Sender := machineID;
1125         out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1126         out_msg.DataBlk := tbe.DataBlk;
1127         out_msg.Dirty := tbe.Dirty;
1128         if (tbe.Shared) {
1129           out_msg.NbReqShared := true;
1130         } else {
1131           out_msg.NbReqShared := false;
1132         }
1133         out_msg.State := CoherenceState:Shared; // faux info
1134         out_msg.MessageSize := MessageSizeType:Writeback_Data;
1135         DPRINTF(RubySlicc, "%s\n", out_msg);
1136       }
1137     }
1138   }
1139
1140   action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") {
1141     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1142       out_msg.addr := address;
1143       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1144       out_msg.Sender := machineID;
1145       // will this always be ok? probably not for multisocket
1146       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1147       out_msg.Dirty := false;
1148       out_msg.Hit := false;
1149       out_msg.Ntsl := true;
1150       out_msg.State := CoherenceState:NA;
1151       out_msg.MessageSize := MessageSizeType:Response_Control;
1152     }
1153   }
1154
1155   action(pim_sendProbeResponseInvMs, "pim", desc="send probe ack inv, no data") {
1156     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1157       out_msg.addr := address;
1158       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1159       out_msg.Sender := machineID;
1160       // will this always be ok? probably not for multisocket
1161       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1162       out_msg.Dirty := false;
1163       out_msg.Ntsl := true;
1164       out_msg.Hit := false;
1165       out_msg.State := CoherenceState:NA;
1166       out_msg.MessageSize := MessageSizeType:Response_Control;
1167     }
1168   }
1169
1170   action(ph_sendProbeResponseHit, "ph", desc="send probe ack PrbShrData, no data") {
1171     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1172       out_msg.addr := address;
1173       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1174       out_msg.Sender := machineID;
1175       // will this always be ok? probably not for multisocket
1176       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1177       assert(addressInCore(address) || is_valid(tbe));
1178       out_msg.Dirty := false;  // only true if sending back data i think
1179       out_msg.Hit := true;
1180       out_msg.Ntsl := false;
1181       out_msg.State := CoherenceState:NA;
1182       out_msg.MessageSize := MessageSizeType:Response_Control;
1183     }
1184   }
1185
1186   action(pb_sendProbeResponseBackprobe, "pb", desc="send probe ack PrbShrData, no data, check for L1 residence") {
1187     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1188       out_msg.addr := address;
1189       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1190       out_msg.Sender := machineID;
1191       // will this always be ok? probably not for multisocket
1192       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1193       if (addressInCore(address)) {
1194         out_msg.Hit := true;
1195       } else {
1196         out_msg.Hit := false;
1197       }
1198       out_msg.Dirty := false;  // not sending back data, so def. not dirty
1199       out_msg.Ntsl := false;
1200       out_msg.State := CoherenceState:NA;
1201       out_msg.MessageSize := MessageSizeType:Response_Control;
1202     }
1203   }
1204
1205   action(pd_sendProbeResponseData, "pd", desc="send probe ack, with data") {
1206     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1207       assert(is_valid(cache_entry));
1208       out_msg.addr := address;
1209       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1210       out_msg.Sender := machineID;
1211       // will this always be ok? probably not for multisocket
1212       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1213       out_msg.DataBlk := cache_entry.DataBlk;
1214       assert(cache_entry.Dirty);
1215       out_msg.Dirty := true;
1216       out_msg.Hit := true;
1217       out_msg.State := CoherenceState:NA;
1218       out_msg.MessageSize := MessageSizeType:Response_Data;
1219     }
1220   }
1221
1222   action(pdm_sendProbeResponseDataMs, "pdm", desc="send probe ack, with data") {
1223     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1224       assert(is_valid(cache_entry));
1225       out_msg.addr := address;
1226       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1227       out_msg.Sender := machineID;
1228       // will this always be ok? probably not for multisocket
1229       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1230       out_msg.DataBlk := cache_entry.DataBlk;
1231       assert(cache_entry.Dirty);
1232       out_msg.Dirty := true;
1233       out_msg.Hit := true;
1234       out_msg.State := CoherenceState:NA;
1235       out_msg.MessageSize := MessageSizeType:Response_Data;
1236     }
1237   }
1238
1239   action(pdt_sendProbeResponseDataFromTBE, "pdt", desc="send probe ack with data") {
1240     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1241       assert(is_valid(tbe));
1242       out_msg.addr := address;
1243       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1244       out_msg.Sender := machineID;
1245       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1246       out_msg.DataBlk := tbe.DataBlk;
1247       assert(tbe.Dirty);
1248       out_msg.Dirty := true;
1249       out_msg.Hit := true;
1250       out_msg.State := CoherenceState:NA;
1251       out_msg.MessageSize := MessageSizeType:Response_Data;
1252     }
1253   }
1254
1255   action(s_setSharedFlip, "s", desc="hit by shared probe, status may be different") {
1256     assert(is_valid(tbe));
1257     tbe.Shared := true;
1258   }
1259
1260   action(uu_sendUnblock, "uu", desc="state changed, unblock") {
1261     enqueue(unblockNetwork_out, UnblockMsg, issue_latency) {
1262       out_msg.addr := address;
1263       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1264       out_msg.MessageSize := MessageSizeType:Unblock_Control;
1265       DPRINTF(RubySlicc, "%s\n", out_msg);
1266     }
1267   }
1268
1269   action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
1270     ++L2cache.demand_misses;
1271   }
1272
1273   action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
1274     ++L1D0cache.demand_misses;
1275   }
1276
1277   action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
1278     ++L1D1cache.demand_misses;
1279   }
1280
1281   action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
1282     ++L1Icache.demand_misses;
1283   }
1284
1285   action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
1286     probeNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1287   }
1288
1289   action(xx_recycleResponseQueue, "xx", desc="recycle response queue") {
1290     responseToCore_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1291   }
1292
1293   action(zz_recycleMandatoryQueue, "\z", desc="recycle mandatory queue") {
1294     mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1295   }
1296
1297   // END ACTIONS
1298
1299   // BEGIN TRANSITIONS
1300
1301   // transitions from base
1302   transition(I, C0_Load_L1miss, I_E0S) {L1D0TagArrayRead, L2TagArrayRead} {
1303     // track misses, if implemented
1304     // since in I state, L2 miss as well
1305     l2m_profileMiss;
1306     l10m_profileMiss;
1307     a0_allocateL1D;
1308     a2_allocateL2;
1309     i1_invCluster;
1310     ii_invIcache;
1311     n_issueRdBlk;
1312     p_popMandatoryQueue;
1313   }
1314
1315   transition(I, C1_Load_L1miss, I_E1S) {L1D1TagArrayRead, L2TagArrayRead} {
1316     // track misses, if implemented
1317     // since in I state, L2 miss as well
1318     l2m_profileMiss;
1319     l11m_profileMiss;
1320     a1_allocateL1D;
1321     a2_allocateL2;
1322     i0_invCluster;
1323     ii_invIcache;
1324     n_issueRdBlk;
1325     p_popMandatoryQueue;
1326   }
1327
1328   transition(I, Ifetch0_L1miss, S0) {L1ITagArrayRead,L2TagArrayRead} {
1329     // track misses, if implemented
1330     // L2 miss as well
1331     l2m_profileMiss;
1332     l1im_profileMiss;
1333     ai_allocateL1I;
1334     a2_allocateL2;
1335     ib_invBothClusters;
1336     nS_issueRdBlkS;
1337     p_popMandatoryQueue;
1338   }
1339
1340   transition(I, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1341     // track misses, if implemented
1342     // L2 miss as well
1343     l2m_profileMiss;
1344     l1im_profileMiss;
1345     ai_allocateL1I;
1346     a2_allocateL2;
1347     ib_invBothClusters;
1348     nS_issueRdBlkS;
1349     p_popMandatoryQueue;
1350   }
1351
1352   transition(I, C0_Store_L1miss, I_M0) {L1D0TagArrayRead, L2TagArrayRead} {
1353     l2m_profileMiss;
1354     l10m_profileMiss;
1355     a0_allocateL1D;
1356     a2_allocateL2;
1357     i1_invCluster;
1358     ii_invIcache;
1359     nM_issueRdBlkM;
1360     p_popMandatoryQueue;
1361   }
1362
1363   transition(I, C1_Store_L1miss, I_M1) {L1D0TagArrayRead, L2TagArrayRead} {
1364     l2m_profileMiss;
1365     l11m_profileMiss;
1366     a1_allocateL1D;
1367     a2_allocateL2;
1368     i0_invCluster;
1369     ii_invIcache;
1370     nM_issueRdBlkM;
1371     p_popMandatoryQueue;
1372   }
1373
1374   transition(S, C0_Load_L1miss, S_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1375     l10m_profileMiss;
1376     a0_allocateL1D;
1377     f0_L2ToL1;
1378     mru_setMRU;
1379     p_popMandatoryQueue;
1380   }
1381
1382   transition(S, C1_Load_L1miss, S_F1) {L1D1TagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1383     l11m_profileMiss;
1384     a1_allocateL1D;
1385     f1_L2ToL1;
1386     mru_setMRU;
1387     p_popMandatoryQueue;
1388   }
1389
1390   transition(S, Ifetch0_L1miss, Si_F0) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1391     l1im_profileMiss;
1392     ai_allocateL1I;
1393     fi_L2ToL1;
1394     mru_setMRU;
1395     p_popMandatoryQueue;
1396   }
1397
1398   transition(S, Ifetch1_L1miss, Si_F1) {L1ITagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1399     l1im_profileMiss;
1400     ai_allocateL1I;
1401     fi_L2ToL1;
1402     mru_setMRU;
1403     p_popMandatoryQueue;
1404   }
1405
1406   transition({S}, {C0_Store_L1hit, C0_Store_L1miss}, S_M0) {L1D0TagArrayRead, L2TagArrayRead} {
1407     l2m_profileMiss;
1408     l10m_profileMiss;
1409     a0_allocateL1D;
1410     mruD0_setD0cacheMRU;
1411     i1_invCluster;
1412     ii_invIcache;
1413     nM_issueRdBlkM;
1414     p_popMandatoryQueue;
1415   }
1416
1417   transition({S}, {C1_Store_L1hit, C1_Store_L1miss}, S_M1) {L1D1TagArrayRead, L2TagArrayRead} {
1418     l2m_profileMiss;
1419     l11m_profileMiss;
1420     a1_allocateL1D;
1421     mruD1_setD1cacheMRU;
1422     i0_invCluster;
1423     ii_invIcache;
1424     nM_issueRdBlkM;
1425     p_popMandatoryQueue;
1426   }
1427
1428   transition(Es, C0_Load_L1miss, Es_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {  // can this be folded with S_F?
1429     a0_allocateL1D;
1430     l10m_profileMiss;
1431     f0_L2ToL1;
1432     mru_setMRU;
1433     p_popMandatoryQueue;
1434   }
1435
1436   transition(Es, C1_Load_L1miss, Es_F1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {  // can this be folded with S_F?
1437     l11m_profileMiss;
1438     a1_allocateL1D;
1439     f1_L2ToL1;
1440     mru_setMRU;
1441     p_popMandatoryQueue;
1442   }
1443
1444   transition(Es, Ifetch0_L1miss, S0) {L1ITagArrayRead, L1ITagArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
1445     l1im_profileMiss;
1446     i2_invL2;
1447     ai_allocateL1I;
1448     a2_allocateL2;
1449     ib_invBothClusters;
1450     nS_issueRdBlkS;
1451     p_popMandatoryQueue;
1452   }
1453
1454   transition(Es, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1455     l1im_profileMiss;
1456     i2_invL2;
1457     ai_allocateL1I;
1458     a2_allocateL2;
1459     ib_invBothClusters;
1460     nS_issueRdBlkS;
1461     p_popMandatoryQueue;
1462   }
1463
1464   // THES SHOULD NOT BE INSTANTANEOUS BUT OH WELL FOR NOW
1465   transition(Es, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1466     a0_allocateL1D;
1467     i1_invCluster;
1468     s0_storeDone;   // instantaneous L1/L2 dirty - no writethrough delay
1469     mruD0_setD0cacheMRU;
1470     mru_setMRU;
1471     p_popMandatoryQueue;
1472   }
1473
1474   transition(Es, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1475     a1_allocateL1D;
1476     i0_invCluster;
1477     s1_storeDone;
1478     mruD1_setD1cacheMRU;
1479     mru_setMRU;
1480     p_popMandatoryQueue;
1481   }
1482
1483   transition(E0, C0_Load_L1miss, E0_F) {L1D0TagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1484     l10m_profileMiss;
1485     a0_allocateL1D;
1486     f0_L2ToL1;
1487     mru_setMRU;
1488     p_popMandatoryQueue;
1489   }
1490
1491   transition(E0, C1_Load_L1miss, E0_Es) {L1D1TagArrayRead,  L2TagArrayRead, L2DataArrayRead} {
1492     l11m_profileMiss;
1493     a1_allocateL1D;
1494     f1_L2ToL1;
1495     mru_setMRU;
1496     p_popMandatoryQueue;
1497   }
1498
1499   transition(E0, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} {
1500     l2m_profileMiss; // permissions miss, still issue RdBlkS
1501     l1im_profileMiss;
1502     i2_invL2;
1503     ai_allocateL1I;
1504     a2_allocateL2;
1505     i0_invCluster;
1506     nS_issueRdBlkS;
1507     p_popMandatoryQueue;
1508   }
1509
1510   transition(E0, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead} {
1511     l2m_profileMiss; // permissions miss, still issue RdBlkS
1512     l1im_profileMiss;
1513     i2_invL2;
1514     ai_allocateL1I;
1515     a2_allocateL2;
1516     i0_invCluster;
1517     nS_issueRdBlkS;
1518     p_popMandatoryQueue;
1519   }
1520
1521   transition(E0, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1522     a0_allocateL1D;
1523     s0_storeDone;
1524     mruD0_setD0cacheMRU;
1525     mru_setMRU;
1526     p_popMandatoryQueue;
1527   }
1528
1529   transition(E0, C1_Store_L1miss, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1530     l11m_profileMiss;
1531     a1_allocateL1D;
1532     i0_invCluster;
1533     s1_storeDone;
1534     mru_setMRU;
1535     p_popMandatoryQueue;
1536   }
1537
1538   transition(E1, C1_Load_L1miss, E1_F) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1539      l11m_profileMiss;
1540     a1_allocateL1D;
1541     f1_L2ToL1;
1542     mru_setMRU;
1543     p_popMandatoryQueue;
1544   }
1545
1546   transition(E1, C0_Load_L1miss, E1_Es) {L1D0TagArrayRead,  L2TagArrayRead, L2DataArrayRead} {
1547     l11m_profileMiss;
1548     a0_allocateL1D;
1549     f0_L2ToL1;
1550     mru_setMRU;
1551     p_popMandatoryQueue;
1552   }
1553
1554   transition(E1, Ifetch1_L1miss, S1) {L2TagArrayRead,  L1ITagArrayRead} {
1555     l2m_profileMiss; // permissions miss, still issue RdBlkS
1556     l1im_profileMiss;
1557     i2_invL2;
1558     ai_allocateL1I;
1559     a2_allocateL2;
1560     i1_invCluster;
1561     nS_issueRdBlkS;
1562     p_popMandatoryQueue;
1563   }
1564
1565   transition(E1, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} {
1566     l2m_profileMiss; // permissions miss, still issue RdBlkS
1567     l1im_profileMiss;
1568     i2_invL2;
1569     ai_allocateL1I;
1570     a2_allocateL2;
1571     i1_invCluster;
1572     nS_issueRdBlkS;
1573     p_popMandatoryQueue;
1574   }
1575
1576   transition(E1, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite} {
1577     a1_allocateL1D;
1578     s1_storeDone;
1579     mruD1_setD1cacheMRU;
1580     mru_setMRU;
1581     p_popMandatoryQueue;
1582   }
1583
1584   transition(E1, C0_Store_L1miss, M0) {L1D0TagArrayRead, L2TagArrayRead, L2TagArrayWrite, L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite} {
1585      l10m_profileMiss;
1586     a0_allocateL1D;
1587     i1_invCluster;
1588     s0_storeDone;
1589     mru_setMRU;
1590     p_popMandatoryQueue;
1591   }
1592
1593   transition({O}, {C0_Store_L1hit, C0_Store_L1miss}, O_M0) {L1D0TagArrayRead,L2TagArrayRead} {
1594     l2m_profileMiss; // permissions miss, still issue CtoD
1595     l10m_profileMiss;
1596     a0_allocateL1D;
1597     mruD0_setD0cacheMRU;
1598     i1_invCluster;
1599     ii_invIcache;
1600     nM_issueRdBlkM;
1601     p_popMandatoryQueue;
1602   }
1603
1604   transition({O}, {C1_Store_L1hit, C1_Store_L1miss}, O_M1) {L1D1TagArrayRead, L2TagArrayRead} {
1605     l2m_profileMiss; // permissions miss, still issue RdBlkS
1606      l11m_profileMiss;
1607     a1_allocateL1D;
1608     mruD1_setD1cacheMRU;
1609     i0_invCluster;
1610     ii_invIcache;
1611     nM_issueRdBlkM;
1612     p_popMandatoryQueue;
1613   }
1614
1615   transition(O, C0_Load_L1miss, O_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1616     l10m_profileMiss;
1617     a0_allocateL1D;
1618     f0_L2ToL1;
1619     mru_setMRU;
1620     p_popMandatoryQueue;
1621   }
1622
1623   transition(O, C1_Load_L1miss, O_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1624      l11m_profileMiss;
1625     a1_allocateL1D;
1626     f1_L2ToL1;
1627     mru_setMRU;
1628     p_popMandatoryQueue;
1629   }
1630
1631   transition(Ms, C0_Load_L1miss, Ms_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1632     l10m_profileMiss;
1633     a0_allocateL1D;
1634     f0_L2ToL1;
1635     mru_setMRU;
1636     p_popMandatoryQueue;
1637   }
1638
1639   transition(Ms, C1_Load_L1miss, Ms_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1640     l11m_profileMiss;
1641     a1_allocateL1D;
1642     f1_L2ToL1;
1643     mru_setMRU;
1644     p_popMandatoryQueue;
1645   }
1646
1647   transition({Ms, M0, M1, O}, Ifetch0_L1miss, MO_S0) {L1ITagArrayRead, L2DataArrayRead, L2TagArrayRead} {
1648     l2m_profileMiss;  // permissions miss
1649     l1im_profileMiss;
1650     ai_allocateL1I;
1651     t_allocateTBE;
1652     ib_invBothClusters;
1653     vd_victim;
1654 //    i2_invL2;
1655     p_popMandatoryQueue;
1656   }
1657
1658   transition({Ms, M0, M1, O}, Ifetch1_L1miss, MO_S1) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead } {
1659     l2m_profileMiss;  // permissions miss
1660      l1im_profileMiss;
1661     ai_allocateL1I;
1662     t_allocateTBE;
1663     ib_invBothClusters;
1664     vd_victim;
1665 //    i2_invL2;
1666     p_popMandatoryQueue;
1667   }
1668
1669   transition(Ms, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1670     a0_allocateL1D;
1671     i1_invCluster;
1672     s0_storeDone;
1673     mruD0_setD0cacheMRU;
1674     mru_setMRU;
1675     p_popMandatoryQueue;
1676   }
1677
1678   transition(Ms, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1679     a1_allocateL1D;
1680     i0_invCluster;
1681     s1_storeDone;
1682     mruD1_setD1cacheMRU;
1683     mru_setMRU;
1684     p_popMandatoryQueue;
1685   }
1686
1687   transition(M0, C0_Load_L1miss, M0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1688      l10m_profileMiss;
1689     a0_allocateL1D;
1690     f0_L2ToL1;
1691     mru_setMRU;
1692     p_popMandatoryQueue;
1693   }
1694
1695   transition(M0, C1_Load_L1miss, M0_Ms) {L2TagArrayRead, L2DataArrayRead,L1D0TagArrayRead} {
1696     l11m_profileMiss;
1697     a1_allocateL1D;
1698     f1_L2ToL1;
1699     mru_setMRU;
1700     p_popMandatoryQueue;
1701   }
1702
1703   transition(M0, {C0_Store_L1hit, C0_Store_L1miss}) {L1D0TagArrayRead,L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead} {
1704     a0_allocateL1D;
1705     s0_storeDone;
1706     mruD0_setD0cacheMRU;
1707     mru_setMRU;
1708     p_popMandatoryQueue;
1709   }
1710
1711   transition(M0, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
1712     a1_allocateL1D;
1713     i0_invCluster;
1714     s1_storeDone;
1715     mruD1_setD1cacheMRU;
1716     mru_setMRU;
1717     p_popMandatoryQueue;
1718   }
1719
1720   transition(M1, C0_Load_L1miss, M1_Ms) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1721     l10m_profileMiss;
1722     a0_allocateL1D;
1723     f0_L2ToL1;
1724     mru_setMRU;
1725     p_popMandatoryQueue;
1726   }
1727
1728   transition(M1, C1_Load_L1miss, M1_F) {L1D1TagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1729     a1_allocateL1D;
1730     f1_L2ToL1;
1731     mru_setMRU;
1732     p_popMandatoryQueue;
1733   }
1734
1735   transition(M1, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1736     a0_allocateL1D;
1737     i1_invCluster;
1738     s0_storeDone;
1739     mruD0_setD0cacheMRU;
1740     mru_setMRU;
1741     p_popMandatoryQueue;
1742   }
1743
1744   transition(M1, {C1_Store_L1hit, C1_Store_L1miss}) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayWrite} {
1745     a1_allocateL1D;
1746     s1_storeDone;
1747     mruD1_setD1cacheMRU;
1748     mru_setMRU;
1749     p_popMandatoryQueue;
1750   }
1751
1752   // end transitions from base
1753
1754   // Begin simple hit transitions
1755   transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es,
1756           Ms_F1, M0_Ms}, C0_Load_L1hit) {L1D0TagArrayRead, L1D0DataArrayRead} {
1757     // track hits, if implemented
1758     l0_loadDone;
1759     mruD0_setD0cacheMRU;
1760     p_popMandatoryQueue;
1761   }
1762
1763   transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es,
1764           Ms_F0, M1_Ms}, C1_Load_L1hit) {L1D1TagArrayRead, L1D1DataArrayRead} {
1765     // track hits, if implemented
1766     l1_loadDone;
1767     mruD1_setD1cacheMRU;
1768     p_popMandatoryQueue;
1769   }
1770
1771   transition({S, S_C, S_F0, S_F1, S_F}, Ifetch0_L1hit) {L1ITagArrayRead, L1IDataArrayRead} {
1772     // track hits, if implemented
1773     il0_loadDone;
1774     mruI_setIcacheMRU;
1775     p_popMandatoryQueue;
1776   }
1777
1778   transition({S, S_C, S_F0, S_F1, S_F}, Ifetch1_L1hit) {L1ITagArrayRead, L1IDataArrayWrite} {
1779     // track hits, if implemented
1780     il1_loadDone;
1781     mruI_setIcacheMRU;
1782     p_popMandatoryQueue;
1783   }
1784
1785   // end simple hit transitions
1786
1787   // Transitions from transient states
1788
1789   // recycles
1790   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1791           IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1792           E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, C0_Load_L1hit) {} {
1793     zz_recycleMandatoryQueue;
1794   }
1795
1796   transition({IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M1,
1797           O_M1, S0, S1, I_C, S0_C, S1_C, S_C}, C0_Load_L1miss) {} {
1798     zz_recycleMandatoryQueue;
1799   }
1800
1801   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1802           IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1803           E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, C1_Load_L1hit) {} {
1804     zz_recycleMandatoryQueue;
1805   }
1806
1807   transition({IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M0,
1808           O_M0, S0, S1, I_C, S0_C, S1_C, S_C},  C1_Load_L1miss) {} {
1809     zz_recycleMandatoryQueue;
1810   }
1811
1812   transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, {Ifetch0_L1hit, Ifetch1_L1hit}) {} {
1813     zz_recycleMandatoryQueue;
1814   }
1815
1816   transition({I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES,
1817           IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, ES_I, MO_I, S_F0, S_F1, S_F,
1818           O_F0, O_F1, O_F, S_M0, S_M1, O_M0, O_M1, Es_F0, Es_F1, Es_F, E0_F,
1819           E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, I_C,
1820           S_C}, {Ifetch0_L1miss, Ifetch1_L1miss}) {} {
1821     zz_recycleMandatoryQueue;
1822   }
1823
1824   transition({I_E1S, IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, S_F1, O_F1,
1825           Si_F0, Si_F1, S_M1, O_M1, S0, S1, Es_F1, E1_F, E0_Es, Ms_F1, M0_Ms,
1826           M1_F, I_C, S0_C, S1_C, S_C}, {C0_Store_L1miss}) {} {
1827     zz_recycleMandatoryQueue;
1828   }
1829
1830   transition({I_E0S, IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1 S_F0, O_F0,
1831           Si_F0, Si_F1, S_M0, O_M0, S0, S1, Es_F0, E0_F, E1_Es, Ms_F0, M0_F,
1832           M1_Ms, I_C, S0_C, S1_C, S_C}, {C1_Store_L1miss}) {} {
1833     zz_recycleMandatoryQueue;
1834   }
1835
1836   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1837           IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M0, O_M0, Es_F0, Es_F1, Es_F, E0_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_Ms}, {C0_Store_L1hit}) {} {
1838     zz_recycleMandatoryQueue;
1839   }
1840
1841   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1842           IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M1,
1843           O_M1, Es_F0, Es_F1, Es_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F,
1844           M0_Ms, M1_F, M1_Ms}, {C1_Store_L1hit}) {} {
1845     zz_recycleMandatoryQueue;
1846   }
1847
1848   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1849           IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1850           E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, L1D0_Repl) {} {
1851     zz_recycleMandatoryQueue;
1852   }
1853
1854   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1855           IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1856           E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, L1D1_Repl) {} {
1857     zz_recycleMandatoryQueue;
1858   }
1859
1860   transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, L1I_Repl) {} {
1861     zz_recycleMandatoryQueue;
1862   }
1863
1864   transition({S_C, S0_C, S1_C, S0, S1, Si_F0, Si_F1, I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, S_M0, O_M0, S_M1, O_M1, Es_F0, Es_F1, Es_F, E0_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, MO_S0, MO_S1, IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, L2_Repl) {} {
1865     zz_recycleMandatoryQueue;
1866   }
1867
1868   transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, {NB_AckS,
1869           PrbInvData, PrbInv, PrbShrData}) {} {
1870     yy_recycleProbeQueue;  // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1871   }
1872
1873   transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES}, NB_AckE) {} {
1874     xx_recycleResponseQueue;  // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1875   }
1876
1877   transition({E0_Es, E1_F, Es_F1}, C0_Load_L1miss, Es_F) {L2DataArrayRead} {
1878     l10m_profileMiss;
1879     a0_allocateL1D;
1880     f0_L2ToL1;
1881     p_popMandatoryQueue;
1882   }
1883
1884   transition(S_F1, C0_Load_L1miss, S_F) {L2DataArrayRead} {
1885     l10m_profileMiss;
1886     a0_allocateL1D;
1887     f0_L2ToL1;
1888     p_popMandatoryQueue;
1889   }
1890
1891   transition(O_F1, C0_Load_L1miss, O_F) {L2DataArrayRead} {
1892     l10m_profileMiss;
1893     a0_allocateL1D;
1894     f0_L2ToL1;
1895     p_popMandatoryQueue;
1896   }
1897
1898   transition({Ms_F1, M0_Ms, M1_F}, C0_Load_L1miss, Ms_F) {L2DataArrayRead} {
1899     l10m_profileMiss;
1900     a0_allocateL1D;
1901     f0_L2ToL1;
1902     p_popMandatoryQueue;
1903   }
1904
1905   transition(I_M0, C1_Load_L1miss, I_M0Ms) {} {
1906     l2m_profileMiss;
1907     l11m_profileMiss;
1908     a1_allocateL1D;
1909     mru_setMRU;
1910     p_popMandatoryQueue;
1911   }
1912
1913   transition(I_M1, C0_Load_L1miss, I_M1Ms) {} {
1914     l2m_profileMiss;
1915     l10m_profileMiss;
1916     a0_allocateL1D;
1917     mru_setMRU;
1918     p_popMandatoryQueue;
1919   }
1920
1921   transition(I_M0, C1_Store_L1miss, I_M0M1) {} {
1922     l2m_profileMiss;
1923     l11m_profileMiss;
1924     a1_allocateL1D;
1925     mru_setMRU;
1926     p_popMandatoryQueue;
1927   }
1928
1929   transition(I_M1, C0_Store_L1miss, I_M1M0) {} {
1930     l2m_profileMiss;
1931     l10m_profileMiss;
1932     a0_allocateL1D;
1933     mru_setMRU;
1934     p_popMandatoryQueue;
1935   }
1936
1937   transition(I_E0S, C1_Load_L1miss, I_ES) {} {
1938     l2m_profileMiss;
1939     l11m_profileMiss;
1940     a1_allocateL1D;
1941     p_popMandatoryQueue;
1942   }
1943
1944   transition(I_E1S, C0_Load_L1miss, I_ES) {} {
1945     l2m_profileMiss;
1946     l10m_profileMiss;
1947     a0_allocateL1D;
1948     p_popMandatoryQueue;
1949   }
1950
1951   transition({E1_Es, E0_F, Es_F0}, C1_Load_L1miss, Es_F) {L2DataArrayRead} {
1952     l11m_profileMiss;
1953     a1_allocateL1D;
1954     f1_L2ToL1;
1955     p_popMandatoryQueue;
1956   }
1957
1958   transition(S_F0, C1_Load_L1miss, S_F) {L2DataArrayRead} {
1959     l11m_profileMiss;
1960     a1_allocateL1D;
1961     f1_L2ToL1;
1962     p_popMandatoryQueue;
1963   }
1964
1965   transition(O_F0, C1_Load_L1miss, O_F) {L2DataArrayRead} {
1966     l11m_profileMiss;
1967     a1_allocateL1D;
1968     f1_L2ToL1;
1969     p_popMandatoryQueue;
1970   }
1971
1972   transition({Ms_F0, M1_Ms, M0_F}, C1_Load_L1miss, Ms_F) { L2DataArrayRead} {
1973     l11m_profileMiss;
1974     a1_allocateL1D;
1975     f1_L2ToL1;
1976     p_popMandatoryQueue;
1977   }
1978
1979   transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es, Ms_F1, M0_Ms}, L1D0_Repl) {L1D0TagArrayRead} {
1980     i0_invCluster;
1981   }
1982
1983   transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es, Ms_F0, M1_Ms}, L1D1_Repl) {L1D1TagArrayRead} {
1984     i1_invCluster;
1985   }
1986
1987   transition({S, S_C, S_F0, S_F1}, L1I_Repl) {L1ITagArrayRead} {
1988     ii_invIcache;
1989   }
1990
1991   transition({S, E0, E1, Es}, L2_Repl, ES_I) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead, L1D1TagArrayRead} {
1992     forward_eviction_to_cpu0;
1993     forward_eviction_to_cpu1;
1994     t_allocateTBE;
1995     vc_victim;
1996     ib_invBothClusters;
1997     i2_invL2;
1998     ii_invIcache;
1999   }
2000
2001   transition({Ms, M0, M1, O}, L2_Repl, MO_I) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead, L1D1TagArrayRead} {
2002     forward_eviction_to_cpu0;
2003     forward_eviction_to_cpu1;
2004     t_allocateTBE;
2005     vd_victim;
2006     i2_invL2;
2007     ib_invBothClusters;  // nothing will happen for D0 on M1, vice versa
2008   }
2009
2010   transition(S0, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2011     wi_writeIcache;
2012     xi0_loadDone;
2013     uu_sendUnblock;
2014     pr_popResponseQueue;
2015   }
2016
2017   transition(S1, NB_AckS, S) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2018     wi_writeIcache;
2019     xi1_loadDone;
2020     uu_sendUnblock;
2021     pr_popResponseQueue;
2022   }
2023
2024   transition(S0_C, NB_AckS, S_C) {L1D0DataArrayWrite,L2DataArrayWrite} {
2025     wi_writeIcache;
2026     xi0_loadDone;
2027     uu_sendUnblock;
2028     pr_popResponseQueue;
2029   }
2030
2031   transition(S1_C, NB_AckS, S_C) {L1D1DataArrayWrite, L2DataArrayWrite} {
2032     wi_writeIcache;
2033     xi1_loadDone;
2034     uu_sendUnblock;
2035     pr_popResponseQueue;
2036   }
2037
2038   transition(I_M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2039     w0_writeDcache;
2040     xs0_storeDone;
2041     uu_sendUnblock;
2042     pr_popResponseQueue;
2043   }
2044
2045   transition(I_M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2046     w1_writeDcache;
2047     xs1_storeDone;
2048     uu_sendUnblock;
2049     pr_popResponseQueue;
2050   }
2051
2052   // THESE MO->M1 should not be instantaneous but oh well for now.
2053   transition(I_M0M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2054     w0_writeDcache;
2055     xs0_storeDone;
2056     uu_sendUnblock;
2057     i0_invCluster;
2058     s1_storeDone;
2059     pr_popResponseQueue;
2060   }
2061
2062   transition(I_M1M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2063     w1_writeDcache;
2064     xs1_storeDone;
2065     uu_sendUnblock;
2066     i1_invCluster;
2067     s0_storeDone;
2068     pr_popResponseQueue;
2069   }
2070
2071   // Above shoudl be more like this, which has some latency to xfer to L1
2072   transition(I_M0Ms, NB_AckM, M0_Ms) {L1D0DataArrayWrite,L2DataArrayWrite} {
2073     w0_writeDcache;
2074     xs0_storeDone;
2075     uu_sendUnblock;
2076     f1_L2ToL1;
2077     pr_popResponseQueue;
2078   }
2079
2080   transition(I_M1Ms, NB_AckM, M1_Ms) {L1D1DataArrayWrite, L2DataArrayWrite} {
2081     w1_writeDcache;
2082     xs1_storeDone;
2083     uu_sendUnblock;
2084     f0_L2ToL1;
2085     pr_popResponseQueue;
2086   }
2087
2088   transition(I_E0S, NB_AckE, E0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2089     w0_writeDcache;
2090     xl0_loadDone;
2091     uu_sendUnblock;
2092     pr_popResponseQueue;
2093   }
2094
2095   transition(I_E1S, NB_AckE, E1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2096     w1_writeDcache;
2097     xl1_loadDone;
2098     uu_sendUnblock;
2099     pr_popResponseQueue;
2100   }
2101
2102   transition(I_ES, NB_AckE, Es) {L1D1DataArrayWrite, L1D1TagArrayWrite, L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite } {
2103     w0_writeDcache;
2104     xl0_loadDone;
2105     w1_writeDcache;
2106     xl1_loadDone;
2107     uu_sendUnblock;
2108     pr_popResponseQueue;
2109   }
2110
2111   transition(I_E0S, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2112     w0_writeDcache;
2113     xl0_loadDone;
2114     uu_sendUnblock;
2115     pr_popResponseQueue;
2116   }
2117
2118   transition(I_E1S, NB_AckS, S) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
2119     w1_writeDcache;
2120     xl1_loadDone;
2121     uu_sendUnblock;
2122     pr_popResponseQueue;
2123   }
2124
2125   transition(I_ES, NB_AckS, S) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite,  L2DataArrayWrite} {
2126     w0_writeDcache;
2127     xl0_loadDone;
2128     w1_writeDcache;
2129     xl1_loadDone;
2130     uu_sendUnblock;
2131     pr_popResponseQueue;
2132   }
2133
2134   transition(S_F0, L2_to_L1D0, S) {L1D0TagArrayWrite, L1D0DataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2135     c0_copyL2ToL1;
2136     mru_setMRU;
2137     l0_loadDone;
2138     pt_popTriggerQueue;
2139   }
2140
2141   transition(S_F1, L2_to_L1D1, S) {L1D1TagArrayWrite, L1D1DataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2142     c1_copyL2ToL1;
2143     mru_setMRU;
2144     l1_loadDone;
2145     pt_popTriggerQueue;
2146   }
2147
2148   transition(Si_F0, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2149     ci_copyL2ToL1;
2150     mru_setMRU;
2151     il0_loadDone;
2152     pt_popTriggerQueue;
2153   }
2154
2155   transition(Si_F1, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2156     ci_copyL2ToL1;
2157     mru_setMRU;
2158     il1_loadDone;
2159     pt_popTriggerQueue;
2160   }
2161
2162   transition(S_F, L2_to_L1D0, S_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2163     c0_copyL2ToL1;
2164     mru_setMRU;
2165     l0_loadDone;
2166     pt_popTriggerQueue;
2167   }
2168
2169   transition(S_F, L2_to_L1D1, S_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2170     c1_copyL2ToL1;
2171     mru_setMRU;
2172     l1_loadDone;
2173     pt_popTriggerQueue;
2174   }
2175
2176   transition(O_F0, L2_to_L1D0, O) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2177     c0_copyL2ToL1;
2178     mru_setMRU;
2179     l0_loadDone;
2180     pt_popTriggerQueue;
2181   }
2182
2183   transition(O_F1, L2_to_L1D1, O) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2184     c1_copyL2ToL1;
2185     mru_setMRU;
2186     l1_loadDone;
2187     pt_popTriggerQueue;
2188   }
2189
2190   transition(O_F, L2_to_L1D0, O_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2191     c0_copyL2ToL1;
2192     mru_setMRU;
2193     l0_loadDone;
2194     pt_popTriggerQueue;
2195   }
2196
2197   transition(O_F, L2_to_L1D1, O_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2198     c1_copyL2ToL1;
2199     mru_setMRU;
2200     l1_loadDone;
2201     pt_popTriggerQueue;
2202   }
2203
2204   transition(M1_F, L2_to_L1D1, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2205     c1_copyL2ToL1;
2206     mru_setMRU;
2207     l1_loadDone;
2208     pt_popTriggerQueue;
2209   }
2210
2211   transition(M0_F, L2_to_L1D0, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2212     c0_copyL2ToL1;
2213     mru_setMRU;
2214     l0_loadDone;
2215     pt_popTriggerQueue;
2216   }
2217
2218   transition(Ms_F0, L2_to_L1D0, Ms) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2219     c0_copyL2ToL1;
2220     mru_setMRU;
2221     l0_loadDone;
2222     pt_popTriggerQueue;
2223   }
2224
2225   transition(Ms_F1, L2_to_L1D1, Ms) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2226     c1_copyL2ToL1;
2227     mru_setMRU;
2228     l1_loadDone;
2229     pt_popTriggerQueue;
2230   }
2231
2232   transition(Ms_F, L2_to_L1D0, Ms_F1) {L1D0DataArrayWrite, L2DataArrayRead} {
2233     c0_copyL2ToL1;
2234     mru_setMRU;
2235     l0_loadDone;
2236     pt_popTriggerQueue;
2237   }
2238
2239   transition(Ms_F, L2_to_L1D1, Ms_F0) {L1IDataArrayWrite, L2DataArrayRead} {
2240     c1_copyL2ToL1;
2241     mru_setMRU;
2242     l1_loadDone;
2243     pt_popTriggerQueue;
2244   }
2245
2246   transition(M1_Ms, L2_to_L1D0, Ms) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2247     c0_copyL2ToL1;
2248     mru_setMRU;
2249     l0_loadDone;
2250     pt_popTriggerQueue;
2251   }
2252
2253   transition(M0_Ms, L2_to_L1D1, Ms) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2254     c1_copyL2ToL1;
2255     mru_setMRU;
2256     l1_loadDone;
2257     pt_popTriggerQueue;
2258   }
2259
2260   transition(Es_F0, L2_to_L1D0, Es) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2261     c0_copyL2ToL1;
2262     mru_setMRU;
2263     l0_loadDone;
2264     pt_popTriggerQueue;
2265   }
2266
2267   transition(Es_F1, L2_to_L1D1, Es) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2268     c1_copyL2ToL1;
2269     mru_setMRU;
2270     l1_loadDone;
2271     pt_popTriggerQueue;
2272   }
2273
2274   transition(Es_F, L2_to_L1D0, Es_F1) {L2TagArrayRead, L2DataArrayRead} {
2275     c0_copyL2ToL1;
2276     mru_setMRU;
2277     l0_loadDone;
2278     pt_popTriggerQueue;
2279   }
2280
2281   transition(Es_F, L2_to_L1D1, Es_F0) {L2TagArrayRead, L2DataArrayRead} {
2282     c1_copyL2ToL1;
2283     mru_setMRU;
2284     l1_loadDone;
2285     pt_popTriggerQueue;
2286   }
2287
2288   transition(E0_F, L2_to_L1D0, E0) {L2TagArrayRead, L2DataArrayRead} {
2289     c0_copyL2ToL1;
2290     mru_setMRU;
2291     l0_loadDone;
2292     pt_popTriggerQueue;
2293   }
2294
2295   transition(E1_F, L2_to_L1D1, E1) {L2TagArrayRead, L2DataArrayRead} {
2296     c1_copyL2ToL1;
2297     mru_setMRU;
2298     l1_loadDone;
2299     pt_popTriggerQueue;
2300   }
2301
2302   transition(E1_Es, L2_to_L1D0, Es) {L2TagArrayRead, L2DataArrayRead} {
2303     c0_copyL2ToL1;
2304     mru_setMRU;
2305     l0_loadDone;
2306     pt_popTriggerQueue;
2307   }
2308
2309   transition(E0_Es, L2_to_L1D1, Es) {L2TagArrayRead, L2DataArrayRead} {
2310     c1_copyL2ToL1;
2311     mru_setMRU;
2312     l1_loadDone;
2313     pt_popTriggerQueue;
2314   }
2315
2316   transition(IF_E0S, L2_to_L1D0, I_E0S) {} {
2317     pt_popTriggerQueue;
2318   }
2319
2320   transition(IF_E1S, L2_to_L1D1, I_E1S) {} {
2321     pt_popTriggerQueue;
2322   }
2323
2324   transition(IF_ES, L2_to_L1D0, IF1_ES) {} {
2325     pt_popTriggerQueue;
2326   }
2327
2328   transition(IF_ES, L2_to_L1D1, IF0_ES) {} {
2329     pt_popTriggerQueue;
2330   }
2331
2332   transition(IF0_ES, L2_to_L1D0, I_ES) {} {
2333     pt_popTriggerQueue;
2334   }
2335
2336   transition(IF1_ES, L2_to_L1D1, I_ES) {} {
2337     pt_popTriggerQueue;
2338   }
2339
2340   transition(F_S0, L2_to_L1I, S0) {} {
2341     pt_popTriggerQueue;
2342   }
2343
2344   transition(F_S1, L2_to_L1I, S1) {} {
2345     pt_popTriggerQueue;
2346   }
2347
2348   transition({S_M0, O_M0}, NB_AckM, M0) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2349     mru_setMRU;
2350     xs0_storeDone;
2351     uu_sendUnblock;
2352     pr_popResponseQueue;
2353   }
2354
2355   transition({S_M1, O_M1}, NB_AckM, M1) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2356     mru_setMRU;
2357     xs1_storeDone;
2358     uu_sendUnblock;
2359     pr_popResponseQueue;
2360   }
2361
2362   transition(MO_I, NB_AckWB, I) {L2TagArrayWrite} {
2363     wb_data;
2364     d_deallocateTBE;
2365     pr_popResponseQueue;
2366   }
2367
2368   transition(ES_I, NB_AckWB, I) {L2TagArrayWrite} {
2369     wb_data;
2370     d_deallocateTBE;
2371     pr_popResponseQueue;
2372   }
2373
2374   transition(MO_S0, NB_AckWB, S0) {L2TagArrayWrite} {
2375     wb_data;
2376     i2_invL2;
2377     a2_allocateL2;
2378     d_deallocateTBE; // FOO
2379     nS_issueRdBlkS;
2380     pr_popResponseQueue;
2381   }
2382
2383   transition(MO_S1, NB_AckWB, S1) {L2TagArrayWrite} {
2384     wb_data;
2385     i2_invL2;
2386     a2_allocateL2;
2387     d_deallocateTBE; // FOO
2388     nS_issueRdBlkS;
2389     pr_popResponseQueue;
2390   }
2391
2392   // Writeback cancel "ack"
2393   transition(I_C, NB_AckWB, I) {L2TagArrayWrite} {
2394     ss_sendStaleNotification;
2395     d_deallocateTBE;
2396     pr_popResponseQueue;
2397   }
2398
2399   transition(S0_C, NB_AckWB, S0) {L2TagArrayWrite} {
2400     ss_sendStaleNotification;
2401     pr_popResponseQueue;
2402   }
2403
2404   transition(S1_C, NB_AckWB, S1) {L2TagArrayWrite} {
2405     ss_sendStaleNotification;
2406     pr_popResponseQueue;
2407   }
2408
2409   transition(S_C, NB_AckWB, S) {L2TagArrayWrite} {
2410     ss_sendStaleNotification;
2411     pr_popResponseQueue;
2412   }
2413
2414   // Begin Probe Transitions
2415
2416   transition({Ms, M0, M1, O}, PrbInvData, I) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2417     forward_eviction_to_cpu0;
2418     forward_eviction_to_cpu1;
2419     pd_sendProbeResponseData;
2420     i2_invL2;
2421     ib_invBothClusters;
2422     pp_popProbeQueue;
2423   }
2424
2425   transition({Es, E0, E1, S, I}, PrbInvData, I) {L2TagArrayRead, L2TagArrayWrite} {
2426     forward_eviction_to_cpu0;
2427     forward_eviction_to_cpu1;
2428     pi_sendProbeResponseInv;
2429     i2_invL2;
2430     ib_invBothClusters;
2431     ii_invIcache;  // only relevant for S
2432     pp_popProbeQueue;
2433   }
2434
2435   transition(S_C, PrbInvData, I_C) {L2TagArrayWrite} {
2436     t_allocateTBE;
2437     forward_eviction_to_cpu0;
2438     forward_eviction_to_cpu1;
2439     pi_sendProbeResponseInv;
2440     i2_invL2;
2441     ib_invBothClusters;
2442     ii_invIcache;
2443     pp_popProbeQueue;
2444   }
2445
2446   transition(I_C, PrbInvData, I_C) {} {
2447     pi_sendProbeResponseInv;
2448     ib_invBothClusters;
2449     pp_popProbeQueue;
2450   }
2451
2452   transition({Ms, M0, M1, O, Es, E0, E1, S, I}, PrbInv, I) {L2TagArrayRead, L2TagArrayWrite} {
2453     forward_eviction_to_cpu0;
2454     forward_eviction_to_cpu1;
2455     pi_sendProbeResponseInv;
2456     i2_invL2; // nothing will happen in I
2457     ib_invBothClusters;
2458     ii_invIcache;
2459     pp_popProbeQueue;
2460   }
2461
2462   transition(S_C, PrbInv, I_C) {L2TagArrayWrite} {
2463     t_allocateTBE;
2464     forward_eviction_to_cpu0;
2465     forward_eviction_to_cpu1;
2466     pi_sendProbeResponseInv;
2467     i2_invL2;
2468     ib_invBothClusters;
2469     ii_invIcache;
2470     pp_popProbeQueue;
2471   }
2472
2473   transition(I_C, PrbInv, I_C) {} {
2474     pi_sendProbeResponseInv;
2475     ib_invBothClusters;
2476     ii_invIcache;
2477     pp_popProbeQueue;
2478   }
2479
2480   transition({Ms, M0, M1, O}, PrbShrData, O) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2481     pd_sendProbeResponseData;
2482     pp_popProbeQueue;
2483   }
2484
2485   transition({Es, E0, E1, S}, PrbShrData, S) {L2TagArrayRead, L2TagArrayWrite} {
2486     ph_sendProbeResponseHit;
2487     pp_popProbeQueue;
2488   }
2489
2490   transition(S_C, PrbShrData) {} {
2491     ph_sendProbeResponseHit;
2492     pp_popProbeQueue;
2493   }
2494
2495   transition({I, I_C}, PrbShrData) {L2TagArrayRead} {
2496     pb_sendProbeResponseBackprobe;
2497     pp_popProbeQueue;
2498   }
2499
2500   transition({I_M0, I_E0S}, {PrbInv, PrbInvData}) {} {
2501     pi_sendProbeResponseInv;
2502     ib_invBothClusters;  // must invalidate current data (only relevant for I_M0)
2503     a0_allocateL1D;  // but make sure there is room for incoming data when it arrives
2504     pp_popProbeQueue;
2505   }
2506
2507   transition({I_M1, I_E1S}, {PrbInv, PrbInvData}) {} {
2508     pi_sendProbeResponseInv;
2509     ib_invBothClusters; // must invalidate current data (only relevant for I_M1)
2510     a1_allocateL1D;  // but make sure there is room for incoming data when it arrives
2511     pp_popProbeQueue;
2512   }
2513
2514   transition({I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_ES}, {PrbInv, PrbInvData, PrbShrData}) {} {
2515     pi_sendProbeResponseInv;
2516     ib_invBothClusters;
2517     a0_allocateL1D;
2518     a1_allocateL1D;
2519     pp_popProbeQueue;
2520   }
2521
2522   transition({I_M0, I_E0S, I_M1, I_E1S}, PrbShrData) {} {
2523     pb_sendProbeResponseBackprobe;
2524     pp_popProbeQueue;
2525   }
2526
2527   transition(ES_I, PrbInvData, I_C) {} {
2528     pi_sendProbeResponseInv;
2529     ib_invBothClusters;
2530     ii_invIcache;
2531     pp_popProbeQueue;
2532   }
2533
2534   transition(MO_I, PrbInvData, I_C) {} {
2535     pdt_sendProbeResponseDataFromTBE;
2536     ib_invBothClusters;
2537     ii_invIcache;
2538     pp_popProbeQueue;
2539   }
2540
2541   transition(MO_I, PrbInv, I_C) {} {
2542     pi_sendProbeResponseInv;
2543     ib_invBothClusters;
2544     ii_invIcache;
2545     pp_popProbeQueue;
2546   }
2547
2548   transition(ES_I, PrbInv, I_C) {} {
2549     pi_sendProbeResponseInv;
2550     ib_invBothClusters;
2551     ii_invIcache;
2552     pp_popProbeQueue;
2553   }
2554
2555   transition(ES_I, PrbShrData, ES_I) {} {
2556     ph_sendProbeResponseHit;
2557     s_setSharedFlip;
2558     pp_popProbeQueue;
2559   }
2560
2561   transition(MO_I, PrbShrData, MO_I) {} {
2562     pdt_sendProbeResponseDataFromTBE;
2563     s_setSharedFlip;
2564     pp_popProbeQueue;
2565   }
2566
2567   transition(MO_S0, PrbInvData, S0_C) {L2TagArrayWrite} {
2568     forward_eviction_to_cpu0;
2569     forward_eviction_to_cpu1;
2570     pdt_sendProbeResponseDataFromTBE;
2571     i2_invL2;
2572     a2_allocateL2;
2573     d_deallocateTBE;
2574     nS_issueRdBlkS;
2575     pp_popProbeQueue;
2576   }
2577
2578   transition(MO_S1, PrbInvData, S1_C) {L2TagArrayWrite} {
2579     forward_eviction_to_cpu0;
2580     forward_eviction_to_cpu1;
2581     pdt_sendProbeResponseDataFromTBE;
2582     i2_invL2;
2583     a2_allocateL2;
2584     d_deallocateTBE;
2585     nS_issueRdBlkS;
2586     pp_popProbeQueue;
2587   }
2588
2589   transition(MO_S0, PrbInv, S0_C) {L2TagArrayWrite} {
2590     forward_eviction_to_cpu0;
2591     forward_eviction_to_cpu1;
2592     pi_sendProbeResponseInv;
2593     i2_invL2;
2594     a2_allocateL2;
2595     d_deallocateTBE;
2596     nS_issueRdBlkS;
2597     pp_popProbeQueue;
2598   }
2599
2600   transition(MO_S1, PrbInv, S1_C) {L2TagArrayWrite} {
2601     forward_eviction_to_cpu0;
2602     forward_eviction_to_cpu1;
2603     pi_sendProbeResponseInv;
2604     i2_invL2;
2605     a2_allocateL2;
2606     d_deallocateTBE;
2607     nS_issueRdBlkS;
2608     pp_popProbeQueue;
2609   }
2610
2611   transition({MO_S0, MO_S1}, PrbShrData) {} {
2612     pdt_sendProbeResponseDataFromTBE;
2613     s_setSharedFlip;
2614     pp_popProbeQueue;
2615   }
2616
2617   transition({S_F0, Es_F0, E0_F, E1_Es}, {PrbInvData, PrbInv}, IF_E0S) {}{
2618     forward_eviction_to_cpu0;
2619     forward_eviction_to_cpu1;
2620     pi_sendProbeResponseInv;
2621     // invalidate everything you've got
2622     ib_invBothClusters;
2623     ii_invIcache;
2624     i2_invL2;
2625     // but make sure you have room for what you need from the fill
2626     a0_allocateL1D;
2627     a2_allocateL2;
2628     n_issueRdBlk;
2629     pp_popProbeQueue;
2630   }
2631
2632   transition({S_F1, Es_F1, E1_F, E0_Es}, {PrbInvData, PrbInv}, IF_E1S) {} {
2633     forward_eviction_to_cpu0;
2634     forward_eviction_to_cpu1;
2635     pi_sendProbeResponseInv;
2636     // invalidate everything you've got
2637     ib_invBothClusters;
2638     ii_invIcache;
2639     i2_invL2;
2640     // but make sure you have room for what you need from the fill
2641     a1_allocateL1D;
2642     a2_allocateL2;
2643     n_issueRdBlk;
2644     pp_popProbeQueue;
2645   }
2646
2647   transition({S_F, Es_F}, {PrbInvData, PrbInv}, IF_ES) {} {
2648     forward_eviction_to_cpu0;
2649     forward_eviction_to_cpu1;
2650     pi_sendProbeResponseInv;
2651     // invalidate everything you've got
2652     ib_invBothClusters;
2653     ii_invIcache;
2654     i2_invL2;
2655     // but make sure you have room for what you need from the fill
2656     a0_allocateL1D;
2657     a1_allocateL1D;
2658     a2_allocateL2;
2659     n_issueRdBlk;
2660     pp_popProbeQueue;
2661   }
2662
2663   transition(Si_F0, {PrbInvData, PrbInv}, F_S0) {} {
2664     forward_eviction_to_cpu0;
2665     forward_eviction_to_cpu1;
2666     pi_sendProbeResponseInv;
2667     ib_invBothClusters;
2668     ii_invIcache;
2669     i2_invL2;
2670     ai_allocateL1I;
2671     a2_allocateL2;
2672     nS_issueRdBlkS;
2673     pp_popProbeQueue;
2674   }
2675
2676   transition(Si_F1, {PrbInvData, PrbInv}, F_S1) {} {
2677     forward_eviction_to_cpu0;
2678     forward_eviction_to_cpu1;
2679     pi_sendProbeResponseInv;
2680     ib_invBothClusters;
2681     ii_invIcache;
2682     i2_invL2;
2683     ai_allocateL1I;
2684     a2_allocateL2;
2685     nS_issueRdBlkS;
2686     pp_popProbeQueue;
2687   }
2688
2689   transition({Es_F0, E0_F, E1_Es}, PrbShrData, S_F0) {} {
2690     ph_sendProbeResponseHit;
2691     pp_popProbeQueue;
2692   }
2693
2694   transition({Es_F1, E1_F, E0_Es}, PrbShrData, S_F1) {} {
2695     ph_sendProbeResponseHit;
2696     pp_popProbeQueue;
2697   }
2698
2699   transition(Es_F, PrbShrData, S_F) {} {
2700     ph_sendProbeResponseHit;
2701     pp_popProbeQueue;
2702   }
2703
2704   transition({S_F0, S_F1, S_F, Si_F0, Si_F1}, PrbShrData) {} {
2705     ph_sendProbeResponseHit;
2706     pp_popProbeQueue;
2707   }
2708
2709   transition(S_M0, PrbInvData, I_M0) {} {
2710     forward_eviction_to_cpu0;
2711     forward_eviction_to_cpu1;
2712     pim_sendProbeResponseInvMs;
2713     ib_invBothClusters;
2714     ii_invIcache;
2715     i2_invL2;
2716     a0_allocateL1D;
2717     a2_allocateL2;
2718     pp_popProbeQueue;
2719   }
2720
2721   transition(O_M0, PrbInvData, I_M0) {L2DataArrayRead} {
2722     forward_eviction_to_cpu0;
2723     forward_eviction_to_cpu1;
2724     pdm_sendProbeResponseDataMs;
2725     ib_invBothClusters;
2726     ii_invIcache;
2727     i2_invL2;
2728     a0_allocateL1D;
2729     a2_allocateL2;
2730     pp_popProbeQueue;
2731   }
2732
2733   transition({S_M0, O_M0}, {PrbInv}, I_M0) {} {
2734     forward_eviction_to_cpu0;
2735     forward_eviction_to_cpu1;
2736     pim_sendProbeResponseInvMs;
2737     ib_invBothClusters;
2738     ii_invIcache;
2739     i2_invL2;
2740     a0_allocateL1D;
2741     a2_allocateL2;
2742     pp_popProbeQueue;
2743   }
2744
2745   transition(S_M1, PrbInvData, I_M1) {} {
2746     forward_eviction_to_cpu0;
2747     forward_eviction_to_cpu1;
2748     pim_sendProbeResponseInvMs;
2749     ib_invBothClusters;
2750     ii_invIcache;
2751     i2_invL2;
2752     a1_allocateL1D;
2753     a2_allocateL2;
2754     pp_popProbeQueue;
2755   }
2756
2757   transition(O_M1, PrbInvData, I_M1) {} {
2758     forward_eviction_to_cpu0;
2759     forward_eviction_to_cpu1;
2760     pdm_sendProbeResponseDataMs;
2761     ib_invBothClusters;
2762     ii_invIcache;
2763     i2_invL2;
2764     a1_allocateL1D;
2765     a2_allocateL2;
2766     pp_popProbeQueue;
2767   }
2768
2769   transition({S_M1, O_M1}, {PrbInv}, I_M1) {} {
2770     forward_eviction_to_cpu0;
2771     forward_eviction_to_cpu1;
2772     pim_sendProbeResponseInvMs;
2773     ib_invBothClusters;
2774     ii_invIcache;
2775     i2_invL2;
2776     a1_allocateL1D;
2777     a2_allocateL2;
2778     pp_popProbeQueue;
2779   }
2780
2781   transition({S0, S0_C}, {PrbInvData, PrbInv}) {} {
2782     forward_eviction_to_cpu0;
2783     forward_eviction_to_cpu1;
2784     pi_sendProbeResponseInv;
2785     ib_invBothClusters;
2786     ii_invIcache;
2787     i2_invL2;
2788     ai_allocateL1I;
2789     a2_allocateL2;
2790     pp_popProbeQueue;
2791   }
2792
2793   transition({S1, S1_C}, {PrbInvData, PrbInv}) {}  {
2794     forward_eviction_to_cpu0;
2795     forward_eviction_to_cpu1;
2796     pi_sendProbeResponseInv;
2797     ib_invBothClusters;
2798     ii_invIcache;
2799     i2_invL2;
2800     ai_allocateL1I;
2801     a2_allocateL2;
2802     pp_popProbeQueue;
2803   }
2804
2805   transition({S_M0, S_M1}, PrbShrData) {} {
2806     ph_sendProbeResponseHit;
2807     pp_popProbeQueue;
2808   }
2809
2810   transition({O_M0, O_M1}, PrbShrData) {L2DataArrayRead} {
2811     pd_sendProbeResponseData;
2812     pp_popProbeQueue;
2813   }
2814
2815   transition({S0, S1, S0_C, S1_C}, PrbShrData) {} {
2816     pb_sendProbeResponseBackprobe;
2817     pp_popProbeQueue;
2818   }
2819
2820   transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInvData, IF_E0S) { L2DataArrayRead} {
2821     forward_eviction_to_cpu0;
2822     forward_eviction_to_cpu1;
2823     pd_sendProbeResponseData;
2824     ib_invBothClusters;
2825     i2_invL2;
2826     a0_allocateL1D;
2827     a2_allocateL2;
2828     n_issueRdBlk;
2829     pp_popProbeQueue;
2830   }
2831
2832   transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInvData, IF_E1S) {L2DataArrayRead} {
2833     forward_eviction_to_cpu0;
2834     forward_eviction_to_cpu1;
2835     pd_sendProbeResponseData;
2836     ib_invBothClusters;
2837     i2_invL2;
2838     a1_allocateL1D;
2839     a2_allocateL2;
2840     n_issueRdBlk;
2841     pp_popProbeQueue;
2842   }
2843
2844   transition({Ms_F, O_F}, PrbInvData, IF_ES) {L2DataArrayRead} {
2845     forward_eviction_to_cpu0;
2846     forward_eviction_to_cpu1;
2847     pd_sendProbeResponseData;
2848     ib_invBothClusters;
2849     i2_invL2;
2850     a0_allocateL1D;
2851     a1_allocateL1D;
2852     a2_allocateL2;
2853     n_issueRdBlk;
2854     pp_popProbeQueue;
2855   }
2856
2857   transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInv, IF_E0S) {} {
2858     forward_eviction_to_cpu0;
2859     forward_eviction_to_cpu1;
2860     pi_sendProbeResponseInv;
2861     ib_invBothClusters;
2862     i2_invL2;
2863     a0_allocateL1D;
2864     a2_allocateL2;
2865     n_issueRdBlk;
2866     pp_popProbeQueue;
2867   }
2868
2869   transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInv, IF_E1S) {} {
2870     forward_eviction_to_cpu0;
2871     forward_eviction_to_cpu1;
2872     pi_sendProbeResponseInv;
2873     ib_invBothClusters;
2874     i2_invL2;
2875     a1_allocateL1D;
2876     a2_allocateL2;
2877     n_issueRdBlk;
2878     pp_popProbeQueue;
2879   }
2880
2881   transition({Ms_F, O_F}, PrbInv, IF_ES) {} {
2882     forward_eviction_to_cpu0;
2883     forward_eviction_to_cpu1;
2884     pi_sendProbeResponseInv;
2885     ib_invBothClusters;
2886     i2_invL2;
2887     a0_allocateL1D;
2888     a1_allocateL1D;
2889     a2_allocateL2;
2890     n_issueRdBlk;
2891     pp_popProbeQueue;
2892   }
2893
2894   transition({Ms_F0, M0_F, M1_Ms}, PrbShrData, O_F0) {L2DataArrayRead} {
2895     pd_sendProbeResponseData;
2896     pp_popProbeQueue;
2897   }
2898
2899   transition({Ms_F1, M1_F, M0_Ms}, PrbShrData, O_F1) {} {
2900   }
2901
2902   transition({Ms_F}, PrbShrData, O_F) {L2DataArrayRead} {
2903     pd_sendProbeResponseData;
2904     pp_popProbeQueue;
2905   }
2906
2907   transition({O_F0, O_F1, O_F}, PrbShrData) {L2DataArrayRead} {
2908     pd_sendProbeResponseData;
2909     pp_popProbeQueue;
2910   }
2911
2912   // END TRANSITIONS
2913 }
2914
2915