src/mem/ruby/protocol/RubySlicc_Exports.sm

   1 /*
   2  * Copyright (c) 2019 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
  15  * Copyright (c) 2011 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
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  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 // Declarations of external types that are common to all protocols
  43 external_type(int, primitive="yes", default="0");
  44 external_type(bool, primitive="yes", default="false");
  45 external_type(std::string, primitive="yes");
  46 external_type(uint32_t, primitive="yes");
  47 external_type(uint64_t, primitive="yes");
  48 external_type(PacketPtr, primitive="yes");
  49 external_type(Packet, primitive="yes");
  50 external_type(Addr, primitive="yes");
  51 external_type(Cycles, primitive="yes", default="Cycles(0)");
  52 external_type(Tick, primitive="yes", default="0");
  53
  54 structure(WriteMask, external="yes", desc="...") {
  55   void clear();
  56   bool cmpMask(WriteMask);
  57   bool isEmpty();
  58   bool isFull();
  59   bool isOverlap(WriteMask);
  60   void orMask(WriteMask);
  61   void fillMask();
  62 }
  63
  64 structure(DataBlock, external = "yes", desc="..."){
  65   void clear();
  66   void copyPartial(DataBlock, int, int);
  67   void copyPartial(DataBlock, WriteMask);
  68   void atomicPartial(DataBlock, WriteMask);
  69 }
  70
  71 bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt);
  72 bool testAndReadMask(Addr addr, DataBlock datablk, WriteMask mask, Packet *pkt);
  73 bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt);
  74
  75 // AccessPermission
  76 // The following five states define the access permission of all memory blocks.
  77 // These permissions have multiple uses.  They coordinate locking and
  78 // synchronization primitives, as well as enable functional accesses.
  79 // One should not need to add any additional permission values and it is very
  80 // risky to do so.
  81 enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
  82   // Valid data
  83   Read_Only,  desc="block is Read Only (modulo functional writes)";
  84   Read_Write, desc="block is Read/Write";
  85
  86   // Possibly Invalid data
  87   // The maybe stale permission indicates that accordingly to the protocol,
  88   // there is no guarantee the block contains valid data.  However, functional
  89   // writes should update the block because a dataless PUT request may
  90   // revalidate the block's data.
  91   Maybe_Stale, desc="block can be stale or revalidated by a dataless PUT";
  92   // In Broadcast/Snoop protocols, memory has no idea if it is exclusive owner
  93   // or not of a block, making it hard to make the logic of having only one
  94   // read_write block in the system impossible. This is to allow the memory to
  95   // say, "I have the block" and for the RubyPort logic to know that this is a
  96   // last-resort block if there are no writable copies in the caching hierarchy.
  97   // This is not supposed to be used in directory or token protocols where
  98   // memory/NB has an idea of what is going on in the whole system.
  99   Backing_Store, desc="for memory in Broadcast/Snoop protocols";
 100
 101   // Invalid data
 102   Invalid,    desc="block is in an Invalid base state";
 103   NotPresent, desc="block is NotPresent";
 104   Busy,       desc="block is in a transient state, currently invalid";
 105 }
 106 //HSA scopes
 107 enumeration(HSAScope, desc="...", default="HSAScope_UNSPECIFIED") {
 108   UNSPECIFIED, desc="Unspecified scope";
 109   NOSCOPE,     desc="Explictly unscoped";
 110   WAVEFRONT,   desc="Wavefront scope";
 111   WORKGROUP,   desc="Workgroup scope";
 112   DEVICE,      desc="Device scope";
 113   SYSTEM,      desc="System scope";
 114 }
 115
 116 // HSA segment types
 117 enumeration(HSASegment, desc="...", default="HSASegment_GLOBAL") {
 118   GLOBAL,   desc="Global segment";
 119   GROUP,    desc="Group segment";
 120   PRIVATE,  desc="Private segment";
 121   KERNARG,  desc="Kernarg segment";
 122   READONLY, desc="Readonly segment";
 123   SPILL,    desc="Spill segment";
 124   ARG,      desc="Arg segment";
 125 }
 126
 127 // TesterStatus
 128 enumeration(TesterStatus, desc="...") {
 129   Idle,            desc="Idle";
 130   Action_Pending,  desc="Action Pending";
 131   Ready,           desc="Ready";
 132   Check_Pending,   desc="Check Pending";
 133 }
 134
 135 // InvalidateGeneratorStatus
 136 enumeration(InvalidateGeneratorStatus, desc="...") {
 137   Load_Waiting,    desc="Load waiting to be issued";
 138   Load_Pending,    desc="Load issued";
 139   Inv_Waiting,     desc="Store (invalidate) waiting to be issued";
 140   Inv_Pending,     desc="Store (invalidate) issued";
 141 }
 142
 143 // SeriesRequestGeneratorStatus
 144 enumeration(SeriesRequestGeneratorStatus, desc="...") {
 145   Thinking,        desc="Doing work before next action";
 146   Request_Pending, desc="Request pending";
 147 }
 148
 149 // LockStatus
 150 enumeration(LockStatus, desc="...") {
 151   Unlocked,        desc="Lock is not held";
 152   Locked,          desc="Lock is held";
 153 }
 154
 155 // SequencerStatus
 156 enumeration(SequencerStatus, desc="...") {
 157   Idle,            desc="Idle";
 158   Pending,         desc="Pending";
 159 }
 160
 161 enumeration(TransitionResult, desc="...") {
 162   Valid,         desc="Valid transition";
 163   ResourceStall, desc="Stalled due to insufficient resources";
 164   ProtocolStall, desc="Protocol specified stall";
 165   Reject,        desc="Rejected because of a type mismatch";
 166 }
 167
 168 // RubyRequestType
 169 enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
 170   LD,                desc="Load";
 171   ST,                desc="Store";
 172   ATOMIC,            desc="Atomic Load/Store -- depricated. use ATOMIC_RETURN or ATOMIC_NO_RETURN";
 173   ATOMIC_RETURN,     desc="Atomic Load/Store, return data";
 174   ATOMIC_NO_RETURN,  desc="Atomic Load/Store, do not return data";
 175   IFETCH,            desc="Instruction fetch";
 176   IO,                desc="I/O";
 177   REPLACEMENT,       desc="Replacement";
 178   Load_Linked,       desc="";
 179   Store_Conditional, desc="";
 180   RMW_Read,          desc="";
 181   RMW_Write,         desc="";
 182   Locked_RMW_Read,   desc="";
 183   Locked_RMW_Write,  desc="";
 184   COMMIT,            desc="Commit version";
 185   NULL,              desc="Invalid request type";
 186   FLUSH,             desc="Flush request type";
 187   Release,           desc="Release operation";
 188   Acquire,           desc="Acquire opertion";
 189   AcquireRelease,    desc="Acquire and Release opertion";
 190 }
 191
 192 enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
 193   Default,     desc="Replace this with access_types passed to the DMA Ruby object";
 194   LD,          desc="Load";
 195   ST,          desc="Store";
 196   ATOMIC,      desc="Atomic Load/Store";
 197   REPLACEMENT, desc="Replacement";
 198   FLUSH,       desc="Flush request type";
 199   NULL,        desc="Invalid request type";
 200 }
 201
 202 enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
 203   DataArrayRead,    desc="Read access to the cache's data array";
 204   DataArrayWrite,   desc="Write access to the cache's data array";
 205   TagArrayRead,     desc="Read access to the cache's tag array";
 206   TagArrayWrite,    desc="Write access to the cache's tag array";
 207 }
 208
 209 enumeration(CacheResourceType, desc="...", default="CacheResourceType_NULL") {
 210   DataArray,    desc="Access to the cache's data array";
 211   TagArray,     desc="Access to the cache's tag array";
 212 }
 213
 214 enumeration(DirectoryRequestType, desc="...", default="DirectoryRequestType_NULL") {
 215   Default,    desc="Replace this with access_types passed to the Directory Ruby object";
 216 }
 217
 218 enumeration(DMASequencerRequestType, desc="...", default="DMASequencerRequestType_NULL") {
 219   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 220 }
 221
 222 enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestType_NULL") {
 223   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 224 }
 225
 226
 227 // These are statically defined types of states machines that we can have.
 228 // If you want to add a new machine type, edit this enum.  It is not necessary
 229 // for a protocol to have state machines defined for the all types here.  But
 230 // you cannot use anything other than the ones defined here.  Also, a protocol
 231 // can have only one state machine for a given type.
 232 enumeration(MachineType, desc="...", default="MachineType_NULL") {
 233     L0Cache,     desc="L0 Cache Mach";
 234     L1Cache,     desc="L1 Cache Mach";
 235     L2Cache,     desc="L2 Cache Mach";
 236     L3Cache,     desc="L3 Cache Mach";
 237     Directory,   desc="Directory Mach";
 238     DMA,         desc="DMA Mach";
 239     Collector,   desc="Collector Mach";
 240     L1Cache_wCC, desc="L1 Cache Mach to track cache-to-cache transfer (used for miss latency profile)";
 241     L2Cache_wCC, desc="L2 Cache Mach to track cache-to-cache transfer (used for miss latency profile)";
 242     CorePair,    desc="Cache Mach (2 cores, Private L1Ds, Shared L1I & L2)";
 243     TCP,         desc="GPU L1 Data Cache (Texture Cache per Pipe)";
 244     TCC,         desc="GPU L2 Shared Cache (Texture Cache per Channel)";
 245     TCCdir,      desc="Directory at the GPU L2 Cache (TCC)";
 246     SQC,         desc="GPU L1 Instr Cache (Sequencer Cache)";
 247     RegionDir,   desc="Region-granular directory";
 248     RegionBuffer,desc="Region buffer for CPU and GPU";
 249     NULL,        desc="null mach type";
 250 }
 251
 252 // MessageSizeType
 253 enumeration(MessageSizeType, desc="...") {
 254   Control,    desc="Control Message";
 255   Data,       desc="Data Message";
 256   Request_Control, desc="Request";
 257   Reissue_Control, desc="Reissued request";
 258   Response_Data, desc="data response";
 259   ResponseL2hit_Data, desc="data response";
 260   ResponseLocal_Data, desc="data response";
 261   Response_Control, desc="non-data response";
 262   Writeback_Data, desc="Writeback data";
 263   Writeback_Control, desc="Writeback control";
 264   Broadcast_Control, desc="Broadcast control";
 265   Multicast_Control, desc="Multicast control";
 266   Forwarded_Control, desc="Forwarded control";
 267   Invalidate_Control, desc="Invalidate control";
 268   Unblock_Control, desc="Unblock control";
 269   Persistent_Control, desc="Persistent request activation messages";
 270   Completion_Control, desc="Completion messages";
 271 }
 272
 273 // AccessType
 274 enumeration(AccessType, desc="...") {
 275   Read, desc="Reading from cache";
 276   Write, desc="Writing to cache";
 277 }
 278
 279 // RubyAccessMode
 280 enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
 281   Supervisor, desc="Supervisor mode";
 282   User,       desc="User mode";
 283   Device, desc="Device mode";
 284 }
 285
 286 enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
 287   No,    desc="No, not a prefetch";
 288   Yes,   desc="Yes, a prefetch";
 289   L1_HW, desc="This is a L1 hardware prefetch";
 290   L2_HW, desc="This is a L2 hardware prefetch";
 291 }
 292
 293 // CacheMsg
 294 structure(SequencerMsg, desc="...", interface="Message") {
 295   Addr LineAddress,       desc="Line address for this request";
 296   Addr PhysicalAddress,   desc="Physical address for this request";
 297   SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
 298   Addr ProgramCounter,    desc="Program counter of the instruction that caused the miss";
 299   RubyAccessMode AccessMode, desc="user/supervisor access type";
 300   DataBlock DataBlk,         desc="Data";
 301   int Len,                   desc="size in bytes of access";
 302   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 303   MessageSizeType MessageSize, default="MessageSizeType_Request_Control";
 304
 305   bool functionalRead(Packet *pkt) {
 306     return false;
 307   }
 308
 309   bool functionalWrite(Packet *pkt) {
 310     return testAndWrite(PhysicalAddress, DataBlk, pkt);
 311   }
 312 }
 313
 314 // MaskPredictorType
 315 enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") {
 316   Undefined, desc="Undefined";
 317   AlwaysUnicast, desc="AlwaysUnicast";
 318   TokenD, desc="TokenD";
 319   AlwaysBroadcast, desc="AlwaysBroadcast";
 320   TokenB, desc="TokenB";
 321   TokenNull, desc="TokenNull";
 322   Random, desc="Random";
 323   Pairwise, desc="Pairwise";
 324   Owner, desc="Owner";
 325   BroadcastIfShared, desc="Broadcast-If-Shared";
 326   BroadcastCounter, desc="Broadcast Counter";
 327   Group, desc="Group";
 328   Counter, desc="Counter";
 329   StickySpatial, desc="StickySpatial";
 330   OwnerBroadcast, desc="Owner/Broadcast Hybrid";
 331   OwnerGroup, desc="Owner/Group Hybrid";
 332   OwnerBroadcastMod, desc="Owner/Broadcast Hybrid-Mod";
 333   OwnerGroupMod, desc="Owner/Group Hybrid-Mod";
 334   LastNMasks, desc="Last N Masks";
 335   BandwidthAdaptive, desc="Bandwidth Adaptive";
 336 }
 337
 338 // MaskPredictorIndex
 339 enumeration(MaskPredictorIndex, "MaskPredictorIndex_Undefined", desc="...") {
 340   Undefined, desc="Undefined";
 341   DataBlock, desc="Data Block";
 342   PC, desc="Program Counter";
 343 }
 344
 345 // MaskPredictorTraining
 346 enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="...") {
 347   Undefined, desc="Undefined";
 348   None, desc="None";
 349   Implicit, desc="Implicit";
 350   Explicit, desc="Explicit";
 351   Both, desc="Both";
 352 }
 353
 354 // Request Status
 355 enumeration(RequestStatus, desc="...", default="RequestStatus_NULL")  {
 356   Ready, desc="The sequencer is ready and the request does not alias";
 357   Issued, desc="The sequencer successfully issued the request";
 358   BufferFull, desc="Can not issue because the sequencer is full";
 359   Aliased, desc="This request aliased with a currently outstanding request";
 360   NULL, desc="";
 361 }
 362
 363 // LinkDirection
 364 enumeration(LinkDirection, desc="...") {
 365   In, desc="Inward link direction";
 366   Out, desc="Outward link direction";
 367 }