src/mem/ruby/slicc_interface/AbstractCacheEntry.hh

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * Common base class for a machine node.
  31  */
  32
  33 #ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
  34 #define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
  35
  36 #include <iostream>
  37
  38 #include "base/logging.hh"
  39 #include "mem/protocol/AccessPermission.hh"
  40 #include "mem/ruby/common/Address.hh"
  41 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
  42
  43 class DataBlock;
  44
  45 class AbstractCacheEntry : public AbstractEntry
  46 {
  47   public:
  48     AbstractCacheEntry();
  49     virtual ~AbstractCacheEntry() = 0;
  50
  51     // Get/Set permission of the entry
  52     void changePermission(AccessPermission new_perm);
  53
  54     // The methods below are those called by ruby runtime, add when it
  55     // is absolutely necessary and should all be virtual function.
  56     virtual DataBlock& getDataBlk()
  57     { panic("getDataBlk() not implemented!"); }
  58
  59     int validBlocks;
  60     virtual int& getNumValidBlocks()
  61     {
  62         return validBlocks;
  63     }
  64
  65     // Functions for locking and unlocking the cache entry.  These are required
  66     // for supporting atomic memory accesses.
  67     void setLocked(int context);
  68     void clearLocked();
  69     bool isLocked(int context) const;
  70
  71     void setSetIndex(uint32_t s) { m_set_index = s; }
  72     uint32_t getSetIndex() const { return m_set_index; }
  73
  74     void setWayIndex(uint32_t s) { m_way_index = s; }
  75     uint32_t getWayIndex() const { return m_way_index; }
  76
  77     // Address of this block, required by CacheMemory
  78     Addr m_Address;
  79     // Holds info whether the address is locked.
  80     // Required for implementing LL/SC operations.
  81     int m_locked;
  82
  83   private:
  84     // Set and way coordinates of the entry within the cache memory object.
  85     uint32_t m_set_index;
  86     uint32_t m_way_index;
  87 };
  88
  89 inline std::ostream&
  90 operator<<(std::ostream& out, const AbstractCacheEntry& obj)
  91 {
  92     obj.print(out);
  93     out << std::flush;
  94     return out;
  95 }
  96
  97 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__