src/mem/ruby/slicc_interface/AbstractController.cc

   1 /*
   2  * Copyright (c) 2017 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2011-2014 Mark D. Hill and David A. Wood
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
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  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
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  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "mem/ruby/slicc_interface/AbstractController.hh"
  42
  43 #include "debug/RubyQueue.hh"
  44 #include "mem/protocol/MemoryMsg.hh"
  45 #include "mem/ruby/network/Network.hh"
  46 #include "mem/ruby/system/GPUCoalescer.hh"
  47 #include "mem/ruby/system/RubySystem.hh"
  48 #include "mem/ruby/system/Sequencer.hh"
  49 #include "sim/system.hh"
  50
  51 AbstractController::AbstractController(const Params *p)
  52     : MemObject(p), Consumer(this), m_version(p->version),
  53       m_clusterID(p->cluster_id),
  54       m_masterId(p->system->getMasterId(this)), m_is_blocking(false),
  55       m_number_of_TBEs(p->number_of_TBEs),
  56       m_transitions_per_cycle(p->transitions_per_cycle),
  57       m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
  58       memoryPort(csprintf("%s.memory", name()), this, ""),
  59       addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
  60 {
  61     if (m_version == 0) {
  62         // Combine the statistics from all controllers
  63         // of this particular type.
  64         Stats::registerDumpCallback(new StatsCallback(this));
  65     }
  66 }
  67
  68 void
  69 AbstractController::init()
  70 {
  71     params()->ruby_system->registerAbstractController(this);
  72     m_delayHistogram.init(10);
  73     uint32_t size = Network::getNumberOfVirtualNetworks();
  74     for (uint32_t i = 0; i < size; i++) {
  75         m_delayVCHistogram.push_back(new Stats::Histogram());
  76         m_delayVCHistogram[i]->init(10);
  77     }
  78 }
  79
  80 void
  81 AbstractController::resetStats()
  82 {
  83     m_delayHistogram.reset();
  84     uint32_t size = Network::getNumberOfVirtualNetworks();
  85     for (uint32_t i = 0; i < size; i++) {
  86         m_delayVCHistogram[i]->reset();
  87     }
  88 }
  89
  90 void
  91 AbstractController::regStats()
  92 {
  93     MemObject::regStats();
  94
  95     m_fully_busy_cycles
  96         .name(name() + ".fully_busy_cycles")
  97         .desc("cycles for which number of transistions == max transitions")
  98         .flags(Stats::nozero);
  99 }
 100
 101 void
 102 AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
 103 {
 104     assert(virtualNetwork < m_delayVCHistogram.size());
 105     m_delayHistogram.sample(delay);
 106     m_delayVCHistogram[virtualNetwork]->sample(delay);
 107 }
 108
 109 void
 110 AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
 111 {
 112     if (m_waiting_buffers.count(addr) == 0) {
 113         MsgVecType* msgVec = new MsgVecType;
 114         msgVec->resize(m_in_ports, NULL);
 115         m_waiting_buffers[addr] = msgVec;
 116     }
 117     DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
 118             addr);
 119     assert(m_in_ports > m_cur_in_port);
 120     (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
 121 }
 122
 123 void
 124 AbstractController::wakeUpBuffers(Addr addr)
 125 {
 126     if (m_waiting_buffers.count(addr) > 0) {
 127         //
 128         // Wake up all possible lower rank (i.e. lower priority) buffers that could
 129         // be waiting on this message.
 130         //
 131         for (int in_port_rank = m_cur_in_port - 1;
 132              in_port_rank >= 0;
 133              in_port_rank--) {
 134             if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
 135                 (*(m_waiting_buffers[addr]))[in_port_rank]->
 136                     reanalyzeMessages(addr, clockEdge());
 137             }
 138         }
 139         delete m_waiting_buffers[addr];
 140         m_waiting_buffers.erase(addr);
 141     }
 142 }
 143
 144 void
 145 AbstractController::wakeUpAllBuffers(Addr addr)
 146 {
 147     if (m_waiting_buffers.count(addr) > 0) {
 148         //
 149         // Wake up all possible lower rank (i.e. lower priority) buffers that could
 150         // be waiting on this message.
 151         //
 152         for (int in_port_rank = m_in_ports - 1;
 153              in_port_rank >= 0;
 154              in_port_rank--) {
 155             if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
 156                 (*(m_waiting_buffers[addr]))[in_port_rank]->
 157                     reanalyzeMessages(addr, clockEdge());
 158             }
 159         }
 160         delete m_waiting_buffers[addr];
 161         m_waiting_buffers.erase(addr);
 162     }
 163 }
 164
 165 void
 166 AbstractController::wakeUpAllBuffers()
 167 {
 168     //
 169     // Wake up all possible buffers that could be waiting on any message.
 170     //
 171
 172     std::vector<MsgVecType*> wokeUpMsgVecs;
 173     MsgBufType wokeUpMsgBufs;
 174
 175     if (m_waiting_buffers.size() > 0) {
 176         for (WaitingBufType::iterator buf_iter = m_waiting_buffers.begin();
 177              buf_iter != m_waiting_buffers.end();
 178              ++buf_iter) {
 179              for (MsgVecType::iterator vec_iter = buf_iter->second->begin();
 180                   vec_iter != buf_iter->second->end();
 181                   ++vec_iter) {
 182                   //
 183                   // Make sure the MessageBuffer has not already be reanalyzed
 184                   //
 185                   if (*vec_iter != NULL &&
 186                       (wokeUpMsgBufs.count(*vec_iter) == 0)) {
 187                       (*vec_iter)->reanalyzeAllMessages(clockEdge());
 188                       wokeUpMsgBufs.insert(*vec_iter);
 189                   }
 190              }
 191              wokeUpMsgVecs.push_back(buf_iter->second);
 192         }
 193
 194         for (std::vector<MsgVecType*>::iterator wb_iter = wokeUpMsgVecs.begin();
 195              wb_iter != wokeUpMsgVecs.end();
 196              ++wb_iter) {
 197              delete (*wb_iter);
 198         }
 199
 200         m_waiting_buffers.clear();
 201     }
 202 }
 203
 204 void
 205 AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
 206 {
 207     m_is_blocking = true;
 208     m_block_map[addr] = port;
 209 }
 210
 211 bool
 212 AbstractController::isBlocked(Addr addr) const
 213 {
 214     return m_is_blocking && (m_block_map.find(addr) != m_block_map.end());
 215 }
 216
 217 void
 218 AbstractController::unblock(Addr addr)
 219 {
 220     m_block_map.erase(addr);
 221     if (m_block_map.size() == 0) {
 222        m_is_blocking = false;
 223     }
 224 }
 225
 226 bool
 227 AbstractController::isBlocked(Addr addr)
 228 {
 229     return (m_block_map.count(addr) > 0);
 230 }
 231
 232 BaseMasterPort &
 233 AbstractController::getMasterPort(const std::string &if_name,
 234                                   PortID idx)
 235 {
 236     return memoryPort;
 237 }
 238
 239 void
 240 AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
 241                                     Cycles latency)
 242 {
 243     RequestPtr req = std::make_shared<Request>(
 244         addr, RubySystem::getBlockSizeBytes(), 0, m_masterId);
 245
 246     PacketPtr pkt = Packet::createRead(req);
 247     uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()];
 248     pkt->dataDynamic(newData);
 249
 250     SenderState *s = new SenderState(id);
 251     pkt->pushSenderState(s);
 252
 253     // Use functional rather than timing accesses during warmup
 254     if (RubySystem::getWarmupEnabled()) {
 255         memoryPort.sendFunctional(pkt);
 256         recvTimingResp(pkt);
 257         return;
 258     }
 259
 260     memoryPort.schedTimingReq(pkt, clockEdge(latency));
 261 }
 262
 263 void
 264 AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
 265                                      Cycles latency, const DataBlock &block)
 266 {
 267     RequestPtr req = std::make_shared<Request>(
 268         addr, RubySystem::getBlockSizeBytes(), 0, m_masterId);
 269
 270     PacketPtr pkt = Packet::createWrite(req);
 271     pkt->allocate();
 272     pkt->setData(block.getData(0, RubySystem::getBlockSizeBytes()));
 273
 274     SenderState *s = new SenderState(id);
 275     pkt->pushSenderState(s);
 276
 277     // Use functional rather than timing accesses during warmup
 278     if (RubySystem::getWarmupEnabled()) {
 279         memoryPort.sendFunctional(pkt);
 280         recvTimingResp(pkt);
 281         return;
 282     }
 283
 284     // Create a block and copy data from the block.
 285     memoryPort.schedTimingReq(pkt, clockEdge(latency));
 286 }
 287
 288 void
 289 AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
 290                                             Cycles latency,
 291                                             const DataBlock &block, int size)
 292 {
 293     RequestPtr req = std::make_shared<Request>(addr, size, 0, m_masterId);
 294
 295     PacketPtr pkt = Packet::createWrite(req);
 296     pkt->allocate();
 297     pkt->setData(block.getData(getOffset(addr), size));
 298
 299     SenderState *s = new SenderState(id);
 300     pkt->pushSenderState(s);
 301
 302     // Create a block and copy data from the block.
 303     memoryPort.schedTimingReq(pkt, clockEdge(latency));
 304 }
 305
 306 void
 307 AbstractController::functionalMemoryRead(PacketPtr pkt)
 308 {
 309     memoryPort.sendFunctional(pkt);
 310 }
 311
 312 int
 313 AbstractController::functionalMemoryWrite(PacketPtr pkt)
 314 {
 315     int num_functional_writes = 0;
 316
 317     // Check the buffer from the controller to the memory.
 318     if (memoryPort.trySatisfyFunctional(pkt)) {
 319         num_functional_writes++;
 320     }
 321
 322     // Update memory itself.
 323     memoryPort.sendFunctional(pkt);
 324     return num_functional_writes + 1;
 325 }
 326
 327 void
 328 AbstractController::recvTimingResp(PacketPtr pkt)
 329 {
 330     assert(getMemoryQueue());
 331     assert(pkt->isResponse());
 332
 333     std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
 334     (*msg).m_addr = pkt->getAddr();
 335     (*msg).m_Sender = m_machineID;
 336
 337     SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
 338     (*msg).m_OriginalRequestorMachId = s->id;
 339     delete s;
 340
 341     if (pkt->isRead()) {
 342         (*msg).m_Type = MemoryRequestType_MEMORY_READ;
 343         (*msg).m_MessageSize = MessageSizeType_Response_Data;
 344
 345         // Copy data from the packet
 346         (*msg).m_DataBlk.setData(pkt->getPtr<uint8_t>(), 0,
 347                                  RubySystem::getBlockSizeBytes());
 348     } else if (pkt->isWrite()) {
 349         (*msg).m_Type = MemoryRequestType_MEMORY_WB;
 350         (*msg).m_MessageSize = MessageSizeType_Writeback_Control;
 351     } else {
 352         panic("Incorrect packet type received from memory controller!");
 353     }
 354
 355     getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
 356     delete pkt;
 357 }
 358
 359 Tick
 360 AbstractController::recvAtomic(PacketPtr pkt)
 361 {
 362    return ticksToCycles(memoryPort.sendAtomic(pkt));
 363 }
 364
 365 MachineID
 366 AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const
 367 {
 368     NodeID node = m_net_ptr->addressToNodeID(addr, mtype);
 369     MachineID mach = {mtype, node};
 370     return mach;
 371 }
 372
 373 bool
 374 AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt)
 375 {
 376     controller->recvTimingResp(pkt);
 377     return true;
 378 }
 379
 380 AbstractController::MemoryPort::MemoryPort(const std::string &_name,
 381                                            AbstractController *_controller,
 382                                            const std::string &_label)
 383     : QueuedMasterPort(_name, _controller, reqQueue, snoopRespQueue),
 384       reqQueue(*_controller, *this, _label),
 385       snoopRespQueue(*_controller, *this, false, _label),
 386       controller(_controller)
 387 {
 388 }