src/mem/ruby/slicc_interface/AbstractController.hh

   1 /*
   2  * Copyright (c) 2017 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
  42 #define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
  43
  44 #include <exception>
  45 #include <iostream>
  46 #include <string>
  47
  48 #include "base/addr_range.hh"
  49 #include "base/callback.hh"
  50 #include "mem/mem_object.hh"
  51 #include "mem/packet.hh"
  52 #include "mem/protocol/AccessPermission.hh"
  53 #include "mem/qport.hh"
  54 #include "mem/ruby/common/Address.hh"
  55 #include "mem/ruby/common/Consumer.hh"
  56 #include "mem/ruby/common/DataBlock.hh"
  57 #include "mem/ruby/common/Histogram.hh"
  58 #include "mem/ruby/common/MachineID.hh"
  59 #include "mem/ruby/network/MessageBuffer.hh"
  60 #include "mem/ruby/system/CacheRecorder.hh"
  61 #include "params/RubyController.hh"
  62
  63 class Network;
  64 class GPUCoalescer;
  65
  66 // used to communicate that an in_port peeked the wrong message type
  67 class RejectException: public std::exception
  68 {
  69     virtual const char* what() const throw()
  70     { return "Port rejected message based on type"; }
  71 };
  72
  73 class AbstractController : public MemObject, public Consumer
  74 {
  75   public:
  76     typedef RubyControllerParams Params;
  77     AbstractController(const Params *p);
  78     void init();
  79     const Params *params() const { return (const Params *)_params; }
  80
  81     NodeID getVersion() const { return m_machineID.getNum(); }
  82     MachineType getType() const { return m_machineID.getType(); }
  83
  84     void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
  85
  86     // return instance name
  87     void blockOnQueue(Addr, MessageBuffer*);
  88     bool isBlocked(Addr) const;
  89     void unblock(Addr);
  90     bool isBlocked(Addr);
  91
  92     virtual MessageBuffer* getMandatoryQueue() const = 0;
  93     virtual MessageBuffer* getMemoryQueue() const = 0;
  94     virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
  95
  96     virtual void print(std::ostream & out) const = 0;
  97     virtual void wakeup() = 0;
  98     virtual void resetStats() = 0;
  99     virtual void regStats();
 100
 101     virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
 102     virtual Sequencer* getCPUSequencer() const = 0;
 103     virtual GPUCoalescer* getGPUCoalescer() const = 0;
 104
 105     //! These functions are used by ruby system to read/write the data blocks
 106     //! that exist with in the controller.
 107     virtual void functionalRead(const Addr &addr, PacketPtr) = 0;
 108     void functionalMemoryRead(PacketPtr);
 109     //! The return value indicates the number of messages written with the
 110     //! data from the packet.
 111     virtual int functionalWriteBuffers(PacketPtr&) = 0;
 112     virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
 113     int functionalMemoryWrite(PacketPtr);
 114
 115     //! Function for enqueuing a prefetch request
 116     virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
 117     { fatal("Prefetches not implemented!");}
 118
 119     //! Function for collating statistics from all the controllers of this
 120     //! particular type. This function should only be called from the
 121     //! version 0 of this controller type.
 122     virtual void collateStats()
 123     {fatal("collateStats() should be overridden!");}
 124
 125     //! Initialize the message buffers.
 126     virtual void initNetQueues() = 0;
 127
 128     /** A function used to return the port associated with this bus object. */
 129     Port &getPort(const std::string &if_name,
 130                   PortID idx=InvalidPortID);
 131
 132     void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
 133     void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
 134                           const DataBlock &block);
 135     void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
 136                                  const DataBlock &block, int size);
 137     void recvTimingResp(PacketPtr pkt);
 138     Tick recvAtomic(PacketPtr pkt);
 139
 140     const AddrRangeList &getAddrRanges() const { return addrRanges; }
 141
 142   public:
 143     MachineID getMachineID() const { return m_machineID; }
 144
 145     Stats::Histogram& getDelayHist() { return m_delayHistogram; }
 146     Stats::Histogram& getDelayVCHist(uint32_t index)
 147     { return *(m_delayVCHistogram[index]); }
 148
 149     /**
 150      * Map an address to the correct MachineID
 151      *
 152      * This function querries the network for the NodeID of the
 153      * destination for a given request using its address and the type
 154      * of the destination. For example for a request with a given
 155      * address to a directory it will return the MachineID of the
 156      * authorative directory.
 157      *
 158      * @param the destination address
 159      * @param the type of the destination
 160      * @return the MachineID of the destination
 161      */
 162     MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
 163
 164   protected:
 165     //! Profiles original cache requests including PUTs
 166     void profileRequest(const std::string &request);
 167     //! Profiles the delay associated with messages.
 168     void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
 169
 170     void stallBuffer(MessageBuffer* buf, Addr addr);
 171     void wakeUpBuffers(Addr addr);
 172     void wakeUpAllBuffers(Addr addr);
 173     void wakeUpAllBuffers();
 174
 175   protected:
 176     const NodeID m_version;
 177     MachineID m_machineID;
 178     const NodeID m_clusterID;
 179
 180     // MasterID used by some components of gem5.
 181     const MasterID m_masterId;
 182
 183     Network *m_net_ptr;
 184     bool m_is_blocking;
 185     std::map<Addr, MessageBuffer*> m_block_map;
 186
 187     typedef std::vector<MessageBuffer*> MsgVecType;
 188     typedef std::set<MessageBuffer*> MsgBufType;
 189     typedef std::map<Addr, MsgVecType* > WaitingBufType;
 190     WaitingBufType m_waiting_buffers;
 191
 192     unsigned int m_in_ports;
 193     unsigned int m_cur_in_port;
 194     const int m_number_of_TBEs;
 195     const int m_transitions_per_cycle;
 196     const unsigned int m_buffer_size;
 197     Cycles m_recycle_latency;
 198
 199     //! Counter for the number of cycles when the transitions carried out
 200     //! were equal to the maximum allowed
 201     Stats::Scalar m_fully_busy_cycles;
 202
 203     //! Histogram for profiling delay for the messages this controller
 204     //! cares for
 205     Stats::Histogram m_delayHistogram;
 206     std::vector<Stats::Histogram *> m_delayVCHistogram;
 207
 208     //! Callback class used for collating statistics from all the
 209     //! controller of this type.
 210     class StatsCallback : public Callback
 211     {
 212       private:
 213         AbstractController *ctr;
 214
 215       public:
 216         virtual ~StatsCallback() {}
 217         StatsCallback(AbstractController *_ctr) : ctr(_ctr) {}
 218         void process() {ctr->collateStats();}
 219     };
 220
 221     /**
 222      * Port that forwards requests and receives responses from the
 223      * memory controller.  It has a queue of packets not yet sent.
 224      */
 225     class MemoryPort : public QueuedMasterPort
 226     {
 227       private:
 228         // Packet queues used to store outgoing requests and snoop responses.
 229         ReqPacketQueue reqQueue;
 230         SnoopRespPacketQueue snoopRespQueue;
 231
 232         // Controller that operates this port.
 233         AbstractController *controller;
 234
 235       public:
 236         MemoryPort(const std::string &_name, AbstractController *_controller,
 237                    const std::string &_label);
 238
 239         // Function for receiving a timing response from the peer port.
 240         // Currently the pkt is handed to the coherence controller
 241         // associated with this port.
 242         bool recvTimingResp(PacketPtr pkt);
 243     };
 244
 245     /* Master port to the memory controller. */
 246     MemoryPort memoryPort;
 247
 248     // State that is stored in packets sent to the memory controller.
 249     struct SenderState : public Packet::SenderState
 250     {
 251         // Id of the machine from which the request originated.
 252         MachineID id;
 253
 254         SenderState(MachineID _id) : id(_id)
 255         {}
 256     };
 257
 258   private:
 259     /** The address range to which the controller responds on the CPU side. */
 260     const AddrRangeList addrRanges;
 261 };
 262
 263 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__