src/mem/ruby/slicc_interface/AbstractController.hh

   1 /*
   2  * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
  30 #define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
  31
  32 #include <exception>
  33 #include <iostream>
  34 #include <string>
  35
  36 #include "base/callback.hh"
  37 #include "mem/protocol/AccessPermission.hh"
  38 #include "mem/ruby/common/Address.hh"
  39 #include "mem/ruby/common/Consumer.hh"
  40 #include "mem/ruby/common/DataBlock.hh"
  41 #include "mem/ruby/common/Histogram.hh"
  42 #include "mem/ruby/common/MachineID.hh"
  43 #include "mem/ruby/network/MessageBuffer.hh"
  44 #include "mem/ruby/network/Network.hh"
  45 #include "mem/ruby/system/CacheRecorder.hh"
  46 #include "mem/packet.hh"
  47 #include "mem/qport.hh"
  48 #include "params/RubyController.hh"
  49 #include "mem/mem_object.hh"
  50
  51 class Network;
  52
  53 // used to communicate that an in_port peeked the wrong message type
  54 class RejectException: public std::exception
  55 {
  56     virtual const char* what() const throw()
  57     { return "Port rejected message based on type"; }
  58 };
  59
  60 class AbstractController : public MemObject, public Consumer
  61 {
  62   public:
  63     typedef RubyControllerParams Params;
  64     AbstractController(const Params *p);
  65     void init();
  66     const Params *params() const { return (const Params *)_params; }
  67
  68     const NodeID getVersion() const { return m_machineID.getNum(); }
  69     const MachineType getType() const { return m_machineID.getType(); }
  70
  71     void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
  72
  73     // return instance name
  74     void blockOnQueue(Address, MessageBuffer*);
  75     void unblock(Address);
  76
  77     virtual MessageBuffer* getMandatoryQueue() const = 0;
  78     virtual AccessPermission getAccessPermission(const Address& addr) = 0;
  79
  80     virtual void print(std::ostream & out) const = 0;
  81     virtual void wakeup() = 0;
  82     virtual void resetStats() = 0;
  83     virtual void regStats();
  84
  85     virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
  86     virtual Sequencer* getSequencer() const = 0;
  87
  88     //! These functions are used by ruby system to read/write the data blocks
  89     //! that exist with in the controller.
  90     virtual void functionalRead(const Address &addr, PacketPtr) = 0;
  91     void functionalMemoryRead(PacketPtr);
  92     //! The return value indicates the number of messages written with the
  93     //! data from the packet.
  94     virtual int functionalWriteBuffers(PacketPtr&) = 0;
  95     virtual int functionalWrite(const Address &addr, PacketPtr) = 0;
  96     int functionalMemoryWrite(PacketPtr);
  97
  98     //! Function for enqueuing a prefetch request
  99     virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
 100     { fatal("Prefetches not implemented!");}
 101
 102     //! Function for collating statistics from all the controllers of this
 103     //! particular type. This function should only be called from the
 104     //! version 0 of this controller type.
 105     virtual void collateStats()
 106     {fatal("collateStats() should be overridden!");}
 107
 108     //! Set the message buffer with given name.
 109     virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0;
 110
 111     /** A function used to return the port associated with this bus object. */
 112     BaseMasterPort& getMasterPort(const std::string& if_name,
 113                                   PortID idx = InvalidPortID);
 114
 115     void queueMemoryRead(const MachineID &id, Address addr, Cycles latency);
 116     void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency,
 117                           const DataBlock &block);
 118     void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency,
 119                                  const DataBlock &block, int size);
 120     void recvTimingResp(PacketPtr pkt);
 121
 122   public:
 123     MachineID getMachineID() const { return m_machineID; }
 124
 125     Stats::Histogram& getDelayHist() { return m_delayHistogram; }
 126     Stats::Histogram& getDelayVCHist(uint32_t index)
 127     { return *(m_delayVCHistogram[index]); }
 128
 129   protected:
 130     //! Profiles original cache requests including PUTs
 131     void profileRequest(const std::string &request);
 132     //! Profiles the delay associated with messages.
 133     void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
 134
 135     void stallBuffer(MessageBuffer* buf, Address addr);
 136     void wakeUpBuffers(Address addr);
 137     void wakeUpAllBuffers(Address addr);
 138     void wakeUpAllBuffers();
 139
 140   protected:
 141     NodeID m_version;
 142     MachineID m_machineID;
 143     NodeID m_clusterID;
 144
 145     // MasterID used by some components of gem5.
 146     MasterID m_masterId;
 147
 148     Network* m_net_ptr;
 149     bool m_is_blocking;
 150     std::map<Address, MessageBuffer*> m_block_map;
 151
 152     typedef std::vector<MessageBuffer*> MsgVecType;
 153     typedef std::set<MessageBuffer*> MsgBufType;
 154     typedef std::map< Address, MsgVecType* > WaitingBufType;
 155     WaitingBufType m_waiting_buffers;
 156
 157     unsigned int m_in_ports;
 158     unsigned int m_cur_in_port;
 159     int m_number_of_TBEs;
 160     int m_transitions_per_cycle;
 161     unsigned int m_buffer_size;
 162     Cycles m_recycle_latency;
 163
 164     //! Counter for the number of cycles when the transitions carried out
 165     //! were equal to the maximum allowed
 166     Stats::Scalar m_fully_busy_cycles;
 167
 168     //! Histogram for profiling delay for the messages this controller
 169     //! cares for
 170     Stats::Histogram m_delayHistogram;
 171     std::vector<Stats::Histogram *> m_delayVCHistogram;
 172
 173     //! Callback class used for collating statistics from all the
 174     //! controller of this type.
 175     class StatsCallback : public Callback
 176     {
 177       private:
 178         AbstractController *ctr;
 179
 180       public:
 181         virtual ~StatsCallback() {}
 182         StatsCallback(AbstractController *_ctr) : ctr(_ctr) {}
 183         void process() {ctr->collateStats();}
 184     };
 185
 186     /**
 187      * Port that forwards requests and receives responses from the
 188      * memory controller.  It has a queue of packets not yet sent.
 189      */
 190     class MemoryPort : public QueuedMasterPort
 191     {
 192       private:
 193         // Packet queues used to store outgoing requests and snoop responses.
 194         ReqPacketQueue reqQueue;
 195         SnoopRespPacketQueue snoopRespQueue;
 196
 197         // Controller that operates this port.
 198         AbstractController *controller;
 199
 200       public:
 201         MemoryPort(const std::string &_name, AbstractController *_controller,
 202                    const std::string &_label);
 203
 204         // Function for receiving a timing response from the peer port.
 205         // Currently the pkt is handed to the coherence controller
 206         // associated with this port.
 207         bool recvTimingResp(PacketPtr pkt);
 208     };
 209
 210     /* Master port to the memory controller. */
 211     MemoryPort memoryPort;
 212
 213     // Message Buffer for storing the response received from the
 214     // memory controller.
 215     MessageBuffer *m_responseFromMemory_ptr;
 216
 217     // State that is stored in packets sent to the memory controller.
 218     struct SenderState : public Packet::SenderState
 219     {
 220         // Id of the machine from which the request originated.
 221         MachineID id;
 222
 223         SenderState(MachineID _id) : id(_id)
 224         {}
 225     };
 226 };
 227
 228 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__