rubytest: seperated read and write ports.
[gem5.git] / src / mem / ruby / slicc_interface / Controller.py
1 # Copyright (c) 2009 Advanced Micro Devices, Inc.
2 # All rights reserved.
3 #
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5 # modification, are permitted provided that the following conditions are
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11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
14 #
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 #
27 # Authors: Steve Reinhardt
28 # Brad Beckmann
29
30 from m5.params import *
31 from m5.SimObject import SimObject
32
33 class RubyController(SimObject):
34 type = 'RubyController'
35 cxx_class = 'AbstractController'
36 abstract = True
37 version = Param.Int("")
38 cntrl_id = Param.Int("")
39 transitions_per_cycle = \
40 Param.Int(32, "no. of SLICC state machine transitions per cycle")
41 buffer_size = Param.Int(0, "max buffer size 0 means infinite")
42 recycle_latency = Param.Int(10, "")
43 number_of_TBEs = Param.Int(256, "")
44 ruby_system = Param.RubySystem("");