src/mem/ruby/slicc_interface/Controller.py

   1 # Copyright (c) 2017 ARM Limited
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  13 # Copyright (c) 2009 Advanced Micro Devices, Inc.
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  38 #
  39 # Authors: Steve Reinhardt
  40 #          Brad Beckmann
  41
  42 from m5.params import *
  43 from m5.proxy import *
  44 from m5.objects.ClockedObject import ClockedObject
  45
  46 class RubyController(ClockedObject):
  47     type = 'RubyController'
  48     cxx_class = 'AbstractController'
  49     cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
  50     abstract = True
  51     version = Param.Int("")
  52     addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this "
  53                                         "controller responds to")
  54     cluster_id = Param.UInt32(0, "Id of this controller's cluster")
  55
  56     transitions_per_cycle = \
  57         Param.Int(32, "no. of  SLICC state machine transitions per cycle")
  58     buffer_size = Param.UInt32(0, "max buffer size 0 means infinite")
  59
  60     recycle_latency = Param.Cycles(10, "")
  61     number_of_TBEs = Param.Int(256, "")
  62     ruby_system = Param.RubySystem("")
  63
  64     memory = MasterPort("Port for attaching a memory controller")
  65     system = Param.System(Parent.any, "system object parameter")