src/mem/ruby/structures/CacheMemory.hh

   1 /*
   2  * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
  30 #define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
  31
  32 #include <string>
  33 #include <vector>
  34
  35 #include "base/hashmap.hh"
  36 #include "base/statistics.hh"
  37 #include "mem/protocol/CacheRequestType.hh"
  38 #include "mem/protocol/CacheResourceType.hh"
  39 #include "mem/protocol/RubyRequest.hh"
  40 #include "mem/ruby/common/DataBlock.hh"
  41 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
  42 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
  43 #include "mem/ruby/structures/AbstractReplacementPolicy.hh"
  44 #include "mem/ruby/structures/BankedArray.hh"
  45 #include "mem/ruby/system/CacheRecorder.hh"
  46 #include "params/RubyCache.hh"
  47 #include "sim/sim_object.hh"
  48
  49 class CacheMemory : public SimObject
  50 {
  51   public:
  52     typedef RubyCacheParams Params;
  53     CacheMemory(const Params *p);
  54     ~CacheMemory();
  55
  56     void init();
  57
  58     // Public Methods
  59     // perform a cache access and see if we hit or not.  Return true on a hit.
  60     bool tryCacheAccess(const Address& address, RubyRequestType type,
  61                         DataBlock*& data_ptr);
  62
  63     // similar to above, but doesn't require full access check
  64     bool testCacheAccess(const Address& address, RubyRequestType type,
  65                          DataBlock*& data_ptr);
  66
  67     // tests to see if an address is present in the cache
  68     bool isTagPresent(const Address& address) const;
  69
  70     // Returns true if there is:
  71     //   a) a tag match on this address or there is
  72     //   b) an unused line in the same cache "way"
  73     bool cacheAvail(const Address& address) const;
  74
  75     // find an unused entry and sets the tag appropriate for the address
  76     AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
  77     void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
  78     {
  79         allocate(address, new_entry);
  80     }
  81
  82     // Explicitly free up this address
  83     void deallocate(const Address& address);
  84
  85     // Returns with the physical address of the conflicting cache line
  86     Address cacheProbe(const Address& address) const;
  87
  88     // looks an address up in the cache
  89     AbstractCacheEntry* lookup(const Address& address);
  90     const AbstractCacheEntry* lookup(const Address& address) const;
  91
  92     Cycles getLatency() const { return m_latency; }
  93     Cycles getTagLatency() const { return tagArray.getLatency(); }
  94     Cycles getDataLatency() const { return dataArray.getLatency(); }
  95
  96
  97     // Hook for checkpointing the contents of the cache
  98     void recordCacheContents(int cntrl, CacheRecorder* tr) const;
  99
 100     // Set this address to most recently used
 101     void setMRU(const Address& address);
 102
 103     void setLocked (const Address& addr, int context);
 104     void clearLocked (const Address& addr);
 105     bool isLocked (const Address& addr, int context);
 106
 107     // Print cache contents
 108     void print(std::ostream& out) const;
 109     void printData(std::ostream& out) const;
 110
 111     void regStats();
 112     bool checkResourceAvailable(CacheResourceType res, Address addr);
 113     void recordRequestType(CacheRequestType requestType);
 114
 115   public:
 116     Stats::Scalar m_demand_hits;
 117     Stats::Scalar m_demand_misses;
 118     Stats::Formula m_demand_accesses;
 119
 120     Stats::Scalar m_sw_prefetches;
 121     Stats::Scalar m_hw_prefetches;
 122     Stats::Formula m_prefetches;
 123
 124     Stats::Vector m_accessModeType;
 125
 126     Stats::Scalar numDataArrayReads;
 127     Stats::Scalar numDataArrayWrites;
 128     Stats::Scalar numTagArrayReads;
 129     Stats::Scalar numTagArrayWrites;
 130
 131     Stats::Scalar numTagArrayStalls;
 132     Stats::Scalar numDataArrayStalls;
 133
 134   private:
 135     // convert a Address to its location in the cache
 136     int64 addressToCacheSet(const Address& address) const;
 137
 138     // Given a cache tag: returns the index of the tag in a set.
 139     // returns -1 if the tag is not found.
 140     int findTagInSet(int64 line, const Address& tag) const;
 141     int findTagInSetIgnorePermissions(int64 cacheSet,
 142                                       const Address& tag) const;
 143
 144     // Private copy constructor and assignment operator
 145     CacheMemory(const CacheMemory& obj);
 146     CacheMemory& operator=(const CacheMemory& obj);
 147
 148   private:
 149     Cycles m_latency;
 150
 151     // Data Members (m_prefix)
 152     bool m_is_instruction_only_cache;
 153
 154     // The first index is the # of cache lines.
 155     // The second index is the the amount associativity.
 156     m5::hash_map<Address, int> m_tag_index;
 157     std::vector<std::vector<AbstractCacheEntry*> > m_cache;
 158
 159     AbstractReplacementPolicy *m_replacementPolicy_ptr;
 160
 161     BankedArray dataArray;
 162     BankedArray tagArray;
 163
 164     int m_cache_size;
 165     int m_cache_num_sets;
 166     int m_cache_num_set_bits;
 167     int m_cache_assoc;
 168     int m_start_index_bit;
 169     bool m_resource_stalls;
 170 };
 171
 172 std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
 173
 174 #endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__