src/mem/ruby/system/CacheMemory.hh

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * CacheMemory.hh
  31  *
  32  * Description:
  33  *
  34  * $Id: CacheMemory.hh,v 3.7 2004/06/18 20:15:15 beckmann Exp $
  35  *
  36  */
  37
  38 #ifndef CACHEMEMORY_H
  39 #define CACHEMEMORY_H
  40
  41 #include "mem/ruby/common/Global.hh"
  42 #include "mem/protocol/AccessPermission.hh"
  43 #include "mem/ruby/common/Address.hh"
  44 #include "mem/ruby/recorder/CacheRecorder.hh"
  45 #include "mem/protocol/CacheRequestType.hh"
  46 #include "mem/gems_common/Vector.hh"
  47 #include "mem/ruby/common/DataBlock.hh"
  48 #include "mem/protocol/MachineType.hh"
  49 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
  50 #include "mem/ruby/system/PseudoLRUPolicy.hh"
  51 #include "mem/ruby/system/LRUPolicy.hh"
  52 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
  53 #include "mem/ruby/system/System.hh"
  54 #include "mem/ruby/slicc_interface/AbstractController.hh"
  55 #include "mem/ruby/profiler/CacheProfiler.hh"
  56 #include "mem/protocol/CacheMsg.hh"
  57 #include <vector>
  58
  59 class CacheMemory {
  60 public:
  61
  62   // Constructors
  63   CacheMemory(const string & name);
  64   void init(const vector<string> & argv);
  65
  66   // Destructor
  67   ~CacheMemory();
  68
  69   // factory
  70   //  static CacheMemory* createCache(int level, int num, char split_type, AbstractCacheEntry* (*entry_factory)());
  71   //  static CacheMemory* getCache(int cache_id);
  72
  73   // Public Methods
  74   void printConfig(ostream& out);
  75
  76   // perform a cache access and see if we hit or not.  Return true on a hit.
  77   bool tryCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
  78
  79   // similar to above, but doesn't require full access check
  80   bool testCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
  81
  82   // tests to see if an address is present in the cache
  83   bool isTagPresent(const Address& address) const;
  84
  85   // Returns true if there is:
  86   //   a) a tag match on this address or there is
  87   //   b) an unused line in the same cache "way"
  88   bool cacheAvail(const Address& address) const;
  89
  90   // find an unused entry and sets the tag appropriate for the address
  91   void allocate(const Address& address, AbstractCacheEntry* new_entry);
  92
  93   // Explicitly free up this address
  94   void deallocate(const Address& address);
  95
  96   // Returns with the physical address of the conflicting cache line
  97   Address cacheProbe(const Address& address) const;
  98
  99   // looks an address up in the cache
 100   AbstractCacheEntry& lookup(const Address& address);
 101   const AbstractCacheEntry& lookup(const Address& address) const;
 102
 103   // Get/Set permission of cache block
 104   AccessPermission getPermission(const Address& address) const;
 105   void changePermission(const Address& address, AccessPermission new_perm);
 106
 107   int getLatency() const { return m_latency; }
 108
 109   // Hook for checkpointing the contents of the cache
 110   void recordCacheContents(CacheRecorder& tr) const;
 111   void setAsInstructionCache(bool is_icache) { m_is_instruction_only_cache = is_icache; }
 112
 113   // Set this address to most recently used
 114   void setMRU(const Address& address);
 115
 116   void profileMiss(const CacheMsg & msg);
 117
 118   void getMemoryValue(const Address& addr, char* value,
 119                       unsigned int size_in_bytes );
 120   void setMemoryValue(const Address& addr, char* value,
 121                       unsigned int size_in_bytes );
 122
 123   void setLocked (const Address& addr, int context);
 124   void clearLocked (const Address& addr);
 125   bool isLocked (const Address& addr, int context);
 126   // Print cache contents
 127   void print(ostream& out) const;
 128   void printData(ostream& out) const;
 129
 130   void clearStats() const;
 131   void printStats(ostream& out) const;
 132
 133 private:
 134   // Private Methods
 135
 136   // convert a Address to its location in the cache
 137   Index addressToCacheSet(const Address& address) const;
 138
 139   // Given a cache tag: returns the index of the tag in a set.
 140   // returns -1 if the tag is not found.
 141   int findTagInSet(Index line, const Address& tag) const;
 142   int findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const;
 143
 144   // Private copy constructor and assignment operator
 145   CacheMemory(const CacheMemory& obj);
 146   CacheMemory& operator=(const CacheMemory& obj);
 147
 148 private:
 149   const string m_cache_name;
 150   AbstractController* m_controller;
 151   int m_latency;
 152
 153   // Data Members (m_prefix)
 154   bool m_is_instruction_only_cache;
 155   bool m_is_data_only_cache;
 156
 157   // The first index is the # of cache lines.
 158   // The second index is the the amount associativity.
 159   m5::hash_map<Address, int> m_tag_index;
 160   Vector<Vector<AbstractCacheEntry*> > m_cache;
 161   Vector<Vector<int> > m_locked;
 162
 163   AbstractReplacementPolicy *m_replacementPolicy_ptr;
 164
 165   CacheProfiler* m_profiler_ptr;
 166
 167   int m_cache_num_sets;
 168   int m_cache_num_set_bits;
 169   int m_cache_assoc;
 170
 171   static Vector< CacheMemory* > m_all_caches;
 172 };
 173
 174 // Output operator declaration
 175 //ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj);
 176
 177 // ******************* Definitions *******************
 178
 179 // Output operator definition
 180 inline
 181 ostream& operator<<(ostream& out, const CacheMemory& obj)
 182 {
 183   obj.print(out);
 184   out << flush;
 185   return out;
 186 }
 187
 188
 189 // ****************************************************************
 190
 191 inline
 192 CacheMemory::CacheMemory(const string & name)
 193   : m_cache_name(name)
 194 {
 195   m_profiler_ptr = new CacheProfiler(name);
 196 }
 197
 198 inline
 199 void CacheMemory::init(const vector<string> & argv)
 200 {
 201   int cache_size = 0;
 202   string policy;
 203
 204   m_controller = NULL;
 205   for (uint32 i=0; i<argv.size(); i+=2) {
 206     if (argv[i] == "size_kb") {
 207       cache_size = atoi(argv[i+1].c_str());
 208     } else if (argv[i] == "latency") {
 209       m_latency = atoi(argv[i+1].c_str());
 210     } else if (argv[i] == "assoc") {
 211       m_cache_assoc = atoi(argv[i+1].c_str());
 212     } else if (argv[i] == "replacement_policy") {
 213       policy = argv[i+1];
 214     } else if (argv[i] == "controller") {
 215       m_controller = RubySystem::getController(argv[i+1]);
 216     } else {
 217       cerr << "WARNING: CacheMemory: Unknown configuration parameter: " << argv[i] << endl;
 218     }
 219   }
 220
 221   m_cache_num_sets = cache_size / m_cache_assoc;
 222   m_cache_num_set_bits = log_int(m_cache_num_sets);
 223
 224   if(policy == "PSEUDO_LRU")
 225     m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc);
 226   else if (policy == "LRU")
 227     m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc);
 228   else
 229     assert(false);
 230
 231   m_cache.setSize(m_cache_num_sets);
 232   m_locked.setSize(m_cache_num_sets);
 233   for (int i = 0; i < m_cache_num_sets; i++) {
 234     m_cache[i].setSize(m_cache_assoc);
 235     m_locked[i].setSize(m_cache_assoc);
 236     for (int j = 0; j < m_cache_assoc; j++) {
 237       m_cache[i][j] = NULL;
 238       m_locked[i][j] = -1;
 239     }
 240   }
 241 }
 242
 243 inline
 244 CacheMemory::~CacheMemory()
 245 {
 246   if(m_replacementPolicy_ptr != NULL)
 247     delete m_replacementPolicy_ptr;
 248 }
 249
 250 inline
 251 void CacheMemory::printConfig(ostream& out)
 252 {
 253   out << "Cache config: " << m_cache_name << endl;
 254   if (m_controller != NULL)
 255     out << "  controller: " << m_controller->getName() << endl;
 256   out << "  cache_associativity: " << m_cache_assoc << endl;
 257   out << "  num_cache_sets_bits: " << m_cache_num_set_bits << endl;
 258   const int cache_num_sets = 1 << m_cache_num_set_bits;
 259   out << "  num_cache_sets: " << cache_num_sets << endl;
 260   out << "  cache_set_size_bytes: " << cache_num_sets * RubySystem::getBlockSizeBytes() << endl;
 261   out << "  cache_set_size_Kbytes: "
 262       << double(cache_num_sets * RubySystem::getBlockSizeBytes()) / (1<<10) << endl;
 263   out << "  cache_set_size_Mbytes: "
 264       << double(cache_num_sets * RubySystem::getBlockSizeBytes()) / (1<<20) << endl;
 265   out << "  cache_size_bytes: "
 266       << cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc << endl;
 267   out << "  cache_size_Kbytes: "
 268       << double(cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc) / (1<<10) << endl;
 269   out << "  cache_size_Mbytes: "
 270       << double(cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc) / (1<<20) << endl;
 271 }
 272
 273 // PRIVATE METHODS
 274
 275 // convert a Address to its location in the cache
 276 inline
 277 Index CacheMemory::addressToCacheSet(const Address& address) const
 278 {
 279   assert(address == line_address(address));
 280   return address.bitSelect(RubySystem::getBlockSizeBits(), RubySystem::getBlockSizeBits() + m_cache_num_set_bits-1);
 281 }
 282
 283 // Given a cache index: returns the index of the tag in a set.
 284 // returns -1 if the tag is not found.
 285 inline
 286 int CacheMemory::findTagInSet(Index cacheSet, const Address& tag) const
 287 {
 288   assert(tag == line_address(tag));
 289   // search the set for the tags
 290   m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
 291   if (it != m_tag_index.end())
 292     if (m_cache[cacheSet][it->second]->m_Permission != AccessPermission_NotPresent)
 293       return it->second;
 294   return -1; // Not found
 295   /*
 296   for (int i=0; i < m_cache_assoc; i++) {
 297     if ((m_cache[cacheSet][i] != NULL) &&
 298         (m_cache[cacheSet][i]->m_Address == tag) &&
 299         (m_cache[cacheSet][i]->m_Permission != AccessPermission_NotPresent)) {
 300       return i;
 301     }
 302   }
 303   return -1; // Not found
 304   */
 305 }
 306
 307 // Given a cache index: returns the index of the tag in a set.
 308 // returns -1 if the tag is not found.
 309 inline
 310 int CacheMemory::findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const
 311 {
 312   assert(tag == line_address(tag));
 313   // search the set for the tags
 314   m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
 315   if (it != m_tag_index.end())
 316     return it->second;
 317   return -1; // Not found
 318   /*
 319   assert(tag == line_address(tag));
 320   // search the set for the tags
 321   for (int i=0; i < m_cache_assoc; i++) {
 322     if (m_cache[cacheSet][i] != NULL && m_cache[cacheSet][i]->m_Address == tag)
 323       return i;
 324   }
 325   return -1; // Not found
 326   */
 327 }
 328
 329 // PUBLIC METHODS
 330 inline
 331 bool CacheMemory::tryCacheAccess(const Address& address,
 332                                  CacheRequestType type,
 333                                  DataBlock*& data_ptr)
 334 {
 335   assert(address == line_address(address));
 336   DEBUG_EXPR(CACHE_COMP, HighPrio, address);
 337   Index cacheSet = addressToCacheSet(address);
 338   int loc = findTagInSet(cacheSet, address);
 339   if(loc != -1){ // Do we even have a tag match?
 340     AbstractCacheEntry* entry = m_cache[cacheSet][loc];
 341     m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
 342     data_ptr = &(entry->getDataBlk());
 343
 344     if(entry->m_Permission == AccessPermission_Read_Write) {
 345       return true;
 346     }
 347     if ((entry->m_Permission == AccessPermission_Read_Only) &&
 348         (type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) {
 349       return true;
 350     }
 351     // The line must not be accessible
 352   }
 353   data_ptr = NULL;
 354   return false;
 355 }
 356
 357 inline
 358 bool CacheMemory::testCacheAccess(const Address& address,
 359                                   CacheRequestType type,
 360                                   DataBlock*& data_ptr)
 361 {
 362   assert(address == line_address(address));
 363   DEBUG_EXPR(CACHE_COMP, HighPrio, address);
 364   Index cacheSet = addressToCacheSet(address);
 365   int loc = findTagInSet(cacheSet, address);
 366   if(loc != -1){ // Do we even have a tag match?
 367     AbstractCacheEntry* entry = m_cache[cacheSet][loc];
 368     m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
 369     data_ptr = &(entry->getDataBlk());
 370
 371     return (m_cache[cacheSet][loc]->m_Permission != AccessPermission_NotPresent);
 372   }
 373   data_ptr = NULL;
 374   return false;
 375 }
 376
 377 // tests to see if an address is present in the cache
 378 inline
 379 bool CacheMemory::isTagPresent(const Address& address) const
 380 {
 381   assert(address == line_address(address));
 382   Index cacheSet = addressToCacheSet(address);
 383   int location = findTagInSet(cacheSet, address);
 384
 385   if (location == -1) {
 386     // We didn't find the tag
 387     DEBUG_EXPR(CACHE_COMP, LowPrio, address);
 388     DEBUG_MSG(CACHE_COMP, LowPrio, "No tag match");
 389     return false;
 390   }
 391   DEBUG_EXPR(CACHE_COMP, LowPrio, address);
 392   DEBUG_MSG(CACHE_COMP, LowPrio, "found");
 393   return true;
 394 }
 395
 396 // Returns true if there is:
 397 //   a) a tag match on this address or there is
 398 //   b) an unused line in the same cache "way"
 399 inline
 400 bool CacheMemory::cacheAvail(const Address& address) const
 401 {
 402   assert(address == line_address(address));
 403
 404   Index cacheSet = addressToCacheSet(address);
 405
 406   for (int i=0; i < m_cache_assoc; i++) {
 407     AbstractCacheEntry* entry = m_cache[cacheSet][i];
 408     if (entry != NULL) {
 409       if (entry->m_Address == address ||                         // Already in the cache
 410           entry->m_Permission == AccessPermission_NotPresent) {  // We found an empty entry
 411         return true;
 412       }
 413     } else {
 414       return true;
 415     }
 416   }
 417   return false;
 418 }
 419
 420 inline
 421 void CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
 422 {
 423   assert(address == line_address(address));
 424   assert(!isTagPresent(address));
 425   assert(cacheAvail(address));
 426   DEBUG_EXPR(CACHE_COMP, HighPrio, address);
 427
 428   // Find the first open slot
 429   Index cacheSet = addressToCacheSet(address);
 430   for (int i=0; i < m_cache_assoc; i++) {
 431     if (m_cache[cacheSet][i] == NULL ||
 432         m_cache[cacheSet][i]->m_Permission == AccessPermission_NotPresent) {
 433       m_cache[cacheSet][i] = entry;  // Init entry
 434       m_cache[cacheSet][i]->m_Address = address;
 435       m_cache[cacheSet][i]->m_Permission = AccessPermission_Invalid;
 436       m_locked[cacheSet][i] = -1;
 437       m_tag_index[address] = i;
 438
 439       m_replacementPolicy_ptr->touch(cacheSet, i, g_eventQueue_ptr->getTime());
 440
 441       return;
 442     }
 443   }
 444   ERROR_MSG("Allocate didn't find an available entry");
 445 }
 446
 447 inline
 448 void CacheMemory::deallocate(const Address& address)
 449 {
 450   assert(address == line_address(address));
 451   assert(isTagPresent(address));
 452   DEBUG_EXPR(CACHE_COMP, HighPrio, address);
 453   Index cacheSet = addressToCacheSet(address);
 454   int location = findTagInSet(cacheSet, address);
 455   if (location != -1){
 456     delete m_cache[cacheSet][location];
 457     m_cache[cacheSet][location] = NULL;
 458     m_locked[cacheSet][location] = -1;
 459     m_tag_index.erase(address);
 460   }
 461 }
 462
 463 // Returns with the physical address of the conflicting cache line
 464 inline
 465 Address CacheMemory::cacheProbe(const Address& address) const
 466 {
 467   assert(address == line_address(address));
 468   assert(!cacheAvail(address));
 469
 470   Index cacheSet = addressToCacheSet(address);
 471   return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->m_Address;
 472 }
 473
 474 // looks an address up in the cache
 475 inline
 476 AbstractCacheEntry& CacheMemory::lookup(const Address& address)
 477 {
 478   assert(address == line_address(address));
 479   Index cacheSet = addressToCacheSet(address);
 480   int loc = findTagInSet(cacheSet, address);
 481   assert(loc != -1);
 482   return *m_cache[cacheSet][loc];
 483 }
 484
 485 // looks an address up in the cache
 486 inline
 487 const AbstractCacheEntry& CacheMemory::lookup(const Address& address) const
 488 {
 489   assert(address == line_address(address));
 490   Index cacheSet = addressToCacheSet(address);
 491   int loc = findTagInSet(cacheSet, address);
 492   assert(loc != -1);
 493   return *m_cache[cacheSet][loc];
 494 }
 495
 496 inline
 497 AccessPermission CacheMemory::getPermission(const Address& address) const
 498 {
 499   assert(address == line_address(address));
 500   return lookup(address).m_Permission;
 501 }
 502
 503 inline
 504 void CacheMemory::changePermission(const Address& address, AccessPermission new_perm)
 505 {
 506   assert(address == line_address(address));
 507   lookup(address).m_Permission = new_perm;
 508   Index cacheSet = addressToCacheSet(address);
 509   int loc = findTagInSet(cacheSet, address);
 510   m_locked[cacheSet][loc] = -1;
 511   assert(getPermission(address) == new_perm);
 512 }
 513
 514 // Sets the most recently used bit for a cache block
 515 inline
 516 void CacheMemory::setMRU(const Address& address)
 517 {
 518   Index cacheSet;
 519
 520   cacheSet = addressToCacheSet(address);
 521   m_replacementPolicy_ptr->touch(cacheSet,
 522                                  findTagInSet(cacheSet, address),
 523                                  g_eventQueue_ptr->getTime());
 524 }
 525
 526 inline
 527 void CacheMemory::profileMiss(const CacheMsg & msg)
 528 {
 529   m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(),
 530                                 msg.getSize(), msg.getPrefetch());
 531 }
 532
 533 inline
 534 void CacheMemory::recordCacheContents(CacheRecorder& tr) const
 535 {
 536   for (int i = 0; i < m_cache_num_sets; i++) {
 537     for (int j = 0; j < m_cache_assoc; j++) {
 538       AccessPermission perm = m_cache[i][j]->m_Permission;
 539       CacheRequestType request_type = CacheRequestType_NULL;
 540       if (perm == AccessPermission_Read_Only) {
 541         if (m_is_instruction_only_cache) {
 542           request_type = CacheRequestType_IFETCH;
 543         } else {
 544           request_type = CacheRequestType_LD;
 545         }
 546       } else if (perm == AccessPermission_Read_Write) {
 547         request_type = CacheRequestType_ST;
 548       }
 549
 550       if (request_type != CacheRequestType_NULL) {
 551         //        tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address,
 552         //                     Address(0), request_type, m_replacementPolicy_ptr->getLastAccess(i, j));
 553       }
 554     }
 555   }
 556 }
 557
 558 inline
 559 void CacheMemory::print(ostream& out) const
 560 {
 561   out << "Cache dump: " << m_cache_name << endl;
 562   for (int i = 0; i < m_cache_num_sets; i++) {
 563     for (int j = 0; j < m_cache_assoc; j++) {
 564       if (m_cache[i][j] != NULL) {
 565         out << "  Index: " << i
 566             << " way: " << j
 567             << " entry: " << *m_cache[i][j] << endl;
 568       } else {
 569         out << "  Index: " << i
 570             << " way: " << j
 571             << " entry: NULL" << endl;
 572       }
 573     }
 574   }
 575 }
 576
 577 inline
 578 void CacheMemory::printData(ostream& out) const
 579 {
 580   out << "printData() not supported" << endl;
 581 }
 582
 583 inline void CacheMemory::clearStats() const
 584 {
 585   m_profiler_ptr->clearStats();
 586 }
 587
 588 inline
 589 void CacheMemory::printStats(ostream& out) const
 590 {
 591   m_profiler_ptr->printStats(out);
 592 }
 593
 594 inline
 595 void CacheMemory::getMemoryValue(const Address& addr, char* value,
 596                                  unsigned int size_in_bytes ){
 597   AbstractCacheEntry& entry = lookup(line_address(addr));
 598   unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
 599   for(unsigned int i=0; i<size_in_bytes; ++i){
 600     value[i] = entry.getDataBlk().getByte(i + startByte);
 601   }
 602 }
 603
 604 inline
 605 void CacheMemory::setMemoryValue(const Address& addr, char* value,
 606                                  unsigned int size_in_bytes ){
 607   AbstractCacheEntry& entry = lookup(line_address(addr));
 608   unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
 609   assert(size_in_bytes > 0);
 610   for(unsigned int i=0; i<size_in_bytes; ++i){
 611     entry.getDataBlk().setByte(i + startByte, value[i]);
 612   }
 613
 614   //  entry = lookup(line_address(addr));
 615 }
 616
 617 inline
 618 void
 619 CacheMemory::setLocked(const Address& address, int context)
 620 {
 621   assert(address == line_address(address));
 622   Index cacheSet = addressToCacheSet(address);
 623   int loc = findTagInSet(cacheSet, address);
 624   assert(loc != -1);
 625   m_locked[cacheSet][loc] = context;
 626 }
 627
 628 inline
 629 void
 630 CacheMemory::clearLocked(const Address& address)
 631 {
 632   assert(address == line_address(address));
 633   Index cacheSet = addressToCacheSet(address);
 634   int loc = findTagInSet(cacheSet, address);
 635   assert(loc != -1);
 636   m_locked[cacheSet][loc] = -1;
 637 }
 638
 639 inline
 640 bool
 641 CacheMemory::isLocked(const Address& address, int context)
 642 {
 643   assert(address == line_address(address));
 644   Index cacheSet = addressToCacheSet(address);
 645   int loc = findTagInSet(cacheSet, address);
 646   assert(loc != -1);
 647   return m_locked[cacheSet][loc] == context;
 648 }
 649
 650 #endif //CACHEMEMORY_H
 651