src/mem/ruby/system/CacheMemory.hh

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
  30 #define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
  31
  32 #include <iostream>
  33 #include <string>
  34 #include <vector>
  35
  36 #include "base/hashmap.hh"
  37 #include "mem/protocol/AccessPermission.hh"
  38 #include "mem/protocol/CacheMsg.hh"
  39 #include "mem/protocol/CacheRequestType.hh"
  40 #include "mem/protocol/GenericRequestType.hh"
  41 #include "mem/protocol/MachineType.hh"
  42 #include "mem/ruby/common/Address.hh"
  43 #include "mem/ruby/common/DataBlock.hh"
  44 #include "mem/ruby/common/Global.hh"
  45 #include "mem/ruby/profiler/CacheProfiler.hh"
  46 #include "mem/ruby/recorder/CacheRecorder.hh"
  47 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
  48 #include "mem/ruby/slicc_interface/AbstractController.hh"
  49 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
  50 #include "mem/ruby/system/LRUPolicy.hh"
  51 #include "mem/ruby/system/PseudoLRUPolicy.hh"
  52 #include "mem/ruby/system/System.hh"
  53 #include "params/RubyCache.hh"
  54 #include "sim/sim_object.hh"
  55
  56 class CacheMemory : public SimObject
  57 {
  58   public:
  59     typedef RubyCacheParams Params;
  60     CacheMemory(const Params *p);
  61     ~CacheMemory();
  62
  63     void init();
  64
  65     // Public Methods
  66     void printConfig(std::ostream& out);
  67
  68     // perform a cache access and see if we hit or not.  Return true on a hit.
  69     bool tryCacheAccess(const Address& address, CacheRequestType type,
  70                         DataBlock*& data_ptr);
  71
  72     // similar to above, but doesn't require full access check
  73     bool testCacheAccess(const Address& address, CacheRequestType type,
  74                          DataBlock*& data_ptr);
  75
  76     // tests to see if an address is present in the cache
  77     bool isTagPresent(const Address& address) const;
  78
  79     // Returns true if there is:
  80     //   a) a tag match on this address or there is
  81     //   b) an unused line in the same cache "way"
  82     bool cacheAvail(const Address& address) const;
  83
  84     // find an unused entry and sets the tag appropriate for the address
  85     AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
  86
  87     // Explicitly free up this address
  88     void deallocate(const Address& address);
  89
  90     // Returns with the physical address of the conflicting cache line
  91     Address cacheProbe(const Address& address) const;
  92
  93     // looks an address up in the cache
  94     AbstractCacheEntry* lookup(const Address& address);
  95     const AbstractCacheEntry* lookup(const Address& address) const;
  96
  97     int getLatency() const { return m_latency; }
  98
  99     // Hook for checkpointing the contents of the cache
 100     void recordCacheContents(CacheRecorder& tr) const;
 101     void
 102     setAsInstructionCache(bool is_icache)
 103     {
 104         m_is_instruction_only_cache = is_icache;
 105     }
 106
 107     // Set this address to most recently used
 108     void setMRU(const Address& address);
 109
 110     void profileMiss(const CacheMsg & msg);
 111
 112     void profileGenericRequest(GenericRequestType requestType,
 113                                RubyAccessMode accessType,
 114                                PrefetchBit pfBit);
 115
 116     void getMemoryValue(const Address& addr, char* value,
 117                         unsigned int size_in_bytes);
 118     void setMemoryValue(const Address& addr, char* value,
 119                         unsigned int size_in_bytes);
 120
 121     void setLocked (const Address& addr, int context);
 122     void clearLocked (const Address& addr);
 123     bool isLocked (const Address& addr, int context);
 124     // Print cache contents
 125     void print(std::ostream& out) const;
 126     void printData(std::ostream& out) const;
 127
 128     void clearStats() const;
 129     void printStats(std::ostream& out) const;
 130
 131   private:
 132     // convert a Address to its location in the cache
 133     Index addressToCacheSet(const Address& address) const;
 134
 135     // Given a cache tag: returns the index of the tag in a set.
 136     // returns -1 if the tag is not found.
 137     int findTagInSet(Index line, const Address& tag) const;
 138     int findTagInSetIgnorePermissions(Index cacheSet,
 139                                       const Address& tag) const;
 140
 141     // Private copy constructor and assignment operator
 142     CacheMemory(const CacheMemory& obj);
 143     CacheMemory& operator=(const CacheMemory& obj);
 144
 145   private:
 146     const std::string m_cache_name;
 147     int m_latency;
 148
 149     // Data Members (m_prefix)
 150     bool m_is_instruction_only_cache;
 151     bool m_is_data_only_cache;
 152
 153     // The first index is the # of cache lines.
 154     // The second index is the the amount associativity.
 155     m5::hash_map<Address, int> m_tag_index;
 156     std::vector<std::vector<AbstractCacheEntry*> > m_cache;
 157
 158     AbstractReplacementPolicy *m_replacementPolicy_ptr;
 159
 160     CacheProfiler* m_profiler_ptr;
 161
 162     int m_cache_size;
 163     std::string m_policy;
 164     int m_cache_num_sets;
 165     int m_cache_num_set_bits;
 166     int m_cache_assoc;
 167     int m_start_index_bit;
 168 };
 169
 170 #endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
 171