src/mem/ruby/system/CacheMemory.hh

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * CacheMemory.hh
  31  *
  32  * Description:
  33  *
  34  * $Id: CacheMemory.hh,v 3.7 2004/06/18 20:15:15 beckmann Exp $
  35  *
  36  */
  37
  38 #ifndef CACHEMEMORY_H
  39 #define CACHEMEMORY_H
  40
  41 #include "mem/ruby/common/Global.hh"
  42 #include "mem/protocol/AccessPermission.hh"
  43 #include "mem/ruby/common/Address.hh"
  44 #include "mem/ruby/recorder/CacheRecorder.hh"
  45 #include "mem/protocol/CacheRequestType.hh"
  46 #include "mem/gems_common/Vector.hh"
  47 #include "mem/ruby/common/DataBlock.hh"
  48 #include "mem/protocol/MachineType.hh"
  49 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
  50 #include "mem/ruby/system/PseudoLRUPolicy.hh"
  51 #include "mem/ruby/system/LRUPolicy.hh"
  52 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
  53 #include "mem/ruby/system/System.hh"
  54 #include "mem/ruby/slicc_interface/AbstractController.hh"
  55 #include "mem/ruby/profiler/CacheProfiler.hh"
  56 #include "mem/protocol/CacheMsg.hh"
  57 #include <vector>
  58
  59 class CacheMemory {
  60 public:
  61
  62   // Constructors
  63   CacheMemory(const string & name);
  64   void init(const vector<string> & argv);
  65
  66   // Destructor
  67   ~CacheMemory();
  68
  69   // factory
  70   //  static CacheMemory* createCache(int level, int num, char split_type, AbstractCacheEntry* (*entry_factory)());
  71   //  static CacheMemory* getCache(int cache_id);
  72
  73   // Public Methods
  74   void printConfig(ostream& out);
  75
  76   // perform a cache access and see if we hit or not.  Return true on a hit.
  77   bool tryCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
  78
  79   // similar to above, but doesn't require full access check
  80   bool testCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
  81
  82   // tests to see if an address is present in the cache
  83   bool isTagPresent(const Address& address) const;
  84
  85   // Returns true if there is:
  86   //   a) a tag match on this address or there is
  87   //   b) an unused line in the same cache "way"
  88   bool cacheAvail(const Address& address) const;
  89
  90   // find an unused entry and sets the tag appropriate for the address
  91   void allocate(const Address& address, AbstractCacheEntry* new_entry);
  92
  93   // Explicitly free up this address
  94   void deallocate(const Address& address);
  95
  96   // Returns with the physical address of the conflicting cache line
  97   Address cacheProbe(const Address& address) const;
  98
  99   // looks an address up in the cache
 100   AbstractCacheEntry& lookup(const Address& address);
 101   const AbstractCacheEntry& lookup(const Address& address) const;
 102
 103   // Get/Set permission of cache block
 104   AccessPermission getPermission(const Address& address) const;
 105   void changePermission(const Address& address, AccessPermission new_perm);
 106
 107   int getLatency() const { return m_latency; }
 108
 109   // Hook for checkpointing the contents of the cache
 110   void recordCacheContents(CacheRecorder& tr) const;
 111   void setAsInstructionCache(bool is_icache) { m_is_instruction_only_cache = is_icache; }
 112
 113   // Set this address to most recently used
 114   void setMRU(const Address& address);
 115
 116   void profileMiss(const CacheMsg & msg);
 117
 118   void getMemoryValue(const Address& addr, char* value,
 119                       unsigned int size_in_bytes );
 120   void setMemoryValue(const Address& addr, char* value,
 121                       unsigned int size_in_bytes );
 122
 123   void setLocked (const Address& addr, int context);
 124   void clearLocked (const Address& addr);
 125   bool isLocked (const Address& addr, int context);
 126   // Print cache contents
 127   void print(ostream& out) const;
 128   void printData(ostream& out) const;
 129
 130   void clearStats() const;
 131   void printStats(ostream& out) const;
 132
 133 private:
 134   // Private Methods
 135
 136   // convert a Address to its location in the cache
 137   Index addressToCacheSet(const Address& address) const;
 138
 139   // Given a cache tag: returns the index of the tag in a set.
 140   // returns -1 if the tag is not found.
 141   int findTagInSet(Index line, const Address& tag) const;
 142   int findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const;
 143
 144   // Private copy constructor and assignment operator
 145   CacheMemory(const CacheMemory& obj);
 146   CacheMemory& operator=(const CacheMemory& obj);
 147
 148 private:
 149   const string m_cache_name;
 150   AbstractController* m_controller;
 151   int m_latency;
 152
 153   // Data Members (m_prefix)
 154   bool m_is_instruction_only_cache;
 155   bool m_is_data_only_cache;
 156
 157   // The first index is the # of cache lines.
 158   // The second index is the the amount associativity.
 159   m5::hash_map<Address, int> m_tag_index;
 160   Vector<Vector<AbstractCacheEntry*> > m_cache;
 161   Vector<Vector<int> > m_locked;
 162
 163   AbstractReplacementPolicy *m_replacementPolicy_ptr;
 164
 165   CacheProfiler* m_profiler_ptr;
 166
 167   int m_cache_num_sets;
 168   int m_cache_num_set_bits;
 169   int m_cache_assoc;
 170
 171   static Vector< CacheMemory* > m_all_caches;
 172 };
 173
 174 // Output operator declaration
 175 //ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj);
 176
 177 // ******************* Definitions *******************
 178
 179 // Output operator definition
 180 inline
 181 ostream& operator<<(ostream& out, const CacheMemory& obj)
 182 {
 183   obj.print(out);
 184   out << flush;
 185   return out;
 186 }
 187
 188
 189 // ****************************************************************
 190
 191 inline
 192 CacheMemory::CacheMemory(const string & name)
 193   : m_cache_name(name)
 194 {
 195   m_profiler_ptr = new CacheProfiler(name);
 196 }
 197
 198 inline
 199 void CacheMemory::init(const vector<string> & argv)
 200 {
 201   int cache_size = 0;
 202   string policy;
 203
 204   m_controller = NULL;
 205   for (uint32 i=0; i<argv.size(); i+=2) {
 206     if (argv[i] == "size_kb") {
 207       cache_size = atoi(argv[i+1].c_str());
 208     } else if (argv[i] == "latency") {
 209       m_latency = atoi(argv[i+1].c_str());
 210     } else if (argv[i] == "assoc") {
 211       m_cache_assoc = atoi(argv[i+1].c_str());
 212     } else if (argv[i] == "replacement_policy") {
 213       policy = argv[i+1];
 214     } else if (argv[i] == "controller") {
 215       m_controller = RubySystem::getController(argv[i+1]);
 216     } else {
 217       cerr << "WARNING: CacheMemory: Unknown configuration parameter: " << argv[i] << endl;
 218     }
 219   }
 220
 221   int num_lines = (cache_size*1024)/RubySystem::getBlockSizeBytes();
 222   m_cache_num_sets = num_lines / m_cache_assoc;
 223   m_cache_num_set_bits = log_int(m_cache_num_sets);
 224
 225   if(policy == "PSEUDO_LRU")
 226     m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc);
 227   else if (policy == "LRU")
 228     m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc);
 229   else
 230     assert(false);
 231
 232   m_cache.setSize(m_cache_num_sets);
 233   m_locked.setSize(m_cache_num_sets);
 234   for (int i = 0; i < m_cache_num_sets; i++) {
 235     m_cache[i].setSize(m_cache_assoc);
 236     m_locked[i].setSize(m_cache_assoc);
 237     for (int j = 0; j < m_cache_assoc; j++) {
 238       m_cache[i][j] = NULL;
 239       m_locked[i][j] = -1;
 240     }
 241   }
 242 }
 243
 244 inline
 245 CacheMemory::~CacheMemory()
 246 {
 247   if(m_replacementPolicy_ptr != NULL)
 248     delete m_replacementPolicy_ptr;
 249 }
 250
 251 inline
 252 void CacheMemory::printConfig(ostream& out)
 253 {
 254   out << "Cache config: " << m_cache_name << endl;
 255   if (m_controller != NULL)
 256     out << "  controller: " << m_controller->getName() << endl;
 257   out << "  cache_associativity: " << m_cache_assoc << endl;
 258   out << "  num_cache_sets_bits: " << m_cache_num_set_bits << endl;
 259   const int cache_num_sets = 1 << m_cache_num_set_bits;
 260   out << "  num_cache_sets: " << cache_num_sets << endl;
 261   out << "  cache_set_size_bytes: " << cache_num_sets * RubySystem::getBlockSizeBytes() << endl;
 262   out << "  cache_set_size_Kbytes: "
 263       << double(cache_num_sets * RubySystem::getBlockSizeBytes()) / (1<<10) << endl;
 264   out << "  cache_set_size_Mbytes: "
 265       << double(cache_num_sets * RubySystem::getBlockSizeBytes()) / (1<<20) << endl;
 266   out << "  cache_size_bytes: "
 267       << cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc << endl;
 268   out << "  cache_size_Kbytes: "
 269       << double(cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc) / (1<<10) << endl;
 270   out << "  cache_size_Mbytes: "
 271       << double(cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc) / (1<<20) << endl;
 272 }
 273
 274 // PRIVATE METHODS
 275
 276 // convert a Address to its location in the cache
 277 inline
 278 Index CacheMemory::addressToCacheSet(const Address& address) const
 279 {
 280   assert(address == line_address(address));
 281   return address.bitSelect(RubySystem::getBlockSizeBits(), RubySystem::getBlockSizeBits() + m_cache_num_set_bits-1);
 282 }
 283
 284 // Given a cache index: returns the index of the tag in a set.
 285 // returns -1 if the tag is not found.
 286 inline
 287 int CacheMemory::findTagInSet(Index cacheSet, const Address& tag) const
 288 {
 289   assert(tag == line_address(tag));
 290   // search the set for the tags
 291   m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
 292   if (it != m_tag_index.end())
 293     if (m_cache[cacheSet][it->second]->m_Permission != AccessPermission_NotPresent)
 294       return it->second;
 295   return -1; // Not found
 296 }
 297
 298 // Given a cache index: returns the index of the tag in a set.
 299 // returns -1 if the tag is not found.
 300 inline
 301 int CacheMemory::findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const
 302 {
 303   assert(tag == line_address(tag));
 304   // search the set for the tags
 305   m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
 306   if (it != m_tag_index.end())
 307     return it->second;
 308   return -1; // Not found
 309 }
 310
 311 // PUBLIC METHODS
 312 inline
 313 bool CacheMemory::tryCacheAccess(const Address& address,
 314                                  CacheRequestType type,
 315                                  DataBlock*& data_ptr)
 316 {
 317   assert(address == line_address(address));
 318   DEBUG_EXPR(CACHE_COMP, HighPrio, address);
 319   Index cacheSet = addressToCacheSet(address);
 320   int loc = findTagInSet(cacheSet, address);
 321   if(loc != -1){ // Do we even have a tag match?
 322     AbstractCacheEntry* entry = m_cache[cacheSet][loc];
 323     m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
 324     data_ptr = &(entry->getDataBlk());
 325
 326     if(entry->m_Permission == AccessPermission_Read_Write) {
 327       return true;
 328     }
 329     if ((entry->m_Permission == AccessPermission_Read_Only) &&
 330         (type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) {
 331       return true;
 332     }
 333     // The line must not be accessible
 334   }
 335   data_ptr = NULL;
 336   return false;
 337 }
 338
 339 inline
 340 bool CacheMemory::testCacheAccess(const Address& address,
 341                                   CacheRequestType type,
 342                                   DataBlock*& data_ptr)
 343 {
 344   assert(address == line_address(address));
 345   DEBUG_EXPR(CACHE_COMP, HighPrio, address);
 346   Index cacheSet = addressToCacheSet(address);
 347   int loc = findTagInSet(cacheSet, address);
 348   if(loc != -1){ // Do we even have a tag match?
 349     AbstractCacheEntry* entry = m_cache[cacheSet][loc];
 350     m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
 351     data_ptr = &(entry->getDataBlk());
 352
 353     return (m_cache[cacheSet][loc]->m_Permission != AccessPermission_NotPresent);
 354   }
 355   data_ptr = NULL;
 356   return false;
 357 }
 358
 359 // tests to see if an address is present in the cache
 360 inline
 361 bool CacheMemory::isTagPresent(const Address& address) const
 362 {
 363   assert(address == line_address(address));
 364   Index cacheSet = addressToCacheSet(address);
 365   int location = findTagInSet(cacheSet, address);
 366
 367   if (location == -1) {
 368     // We didn't find the tag
 369     DEBUG_EXPR(CACHE_COMP, LowPrio, address);
 370     DEBUG_MSG(CACHE_COMP, LowPrio, "No tag match");
 371     return false;
 372   }
 373   DEBUG_EXPR(CACHE_COMP, LowPrio, address);
 374   DEBUG_MSG(CACHE_COMP, LowPrio, "found");
 375   return true;
 376 }
 377
 378 // Returns true if there is:
 379 //   a) a tag match on this address or there is
 380 //   b) an unused line in the same cache "way"
 381 inline
 382 bool CacheMemory::cacheAvail(const Address& address) const
 383 {
 384   assert(address == line_address(address));
 385
 386   Index cacheSet = addressToCacheSet(address);
 387
 388   for (int i=0; i < m_cache_assoc; i++) {
 389     AbstractCacheEntry* entry = m_cache[cacheSet][i];
 390     if (entry != NULL) {
 391       if (entry->m_Address == address ||                         // Already in the cache
 392           entry->m_Permission == AccessPermission_NotPresent) {  // We found an empty entry
 393         return true;
 394       }
 395     } else {
 396       return true;
 397     }
 398   }
 399   return false;
 400 }
 401
 402 inline
 403 void CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
 404 {
 405   assert(address == line_address(address));
 406   assert(!isTagPresent(address));
 407   assert(cacheAvail(address));
 408   DEBUG_EXPR(CACHE_COMP, HighPrio, address);
 409
 410   // Find the first open slot
 411   Index cacheSet = addressToCacheSet(address);
 412   for (int i=0; i < m_cache_assoc; i++) {
 413     if (m_cache[cacheSet][i] == NULL ||
 414         m_cache[cacheSet][i]->m_Permission == AccessPermission_NotPresent) {
 415       m_cache[cacheSet][i] = entry;  // Init entry
 416       m_cache[cacheSet][i]->m_Address = address;
 417       m_cache[cacheSet][i]->m_Permission = AccessPermission_Invalid;
 418       m_locked[cacheSet][i] = -1;
 419       m_tag_index[address] = i;
 420
 421       m_replacementPolicy_ptr->touch(cacheSet, i, g_eventQueue_ptr->getTime());
 422
 423       return;
 424     }
 425   }
 426   ERROR_MSG("Allocate didn't find an available entry");
 427 }
 428
 429 inline
 430 void CacheMemory::deallocate(const Address& address)
 431 {
 432   assert(address == line_address(address));
 433   assert(isTagPresent(address));
 434   DEBUG_EXPR(CACHE_COMP, HighPrio, address);
 435   Index cacheSet = addressToCacheSet(address);
 436   int location = findTagInSet(cacheSet, address);
 437   if (location != -1){
 438     delete m_cache[cacheSet][location];
 439     m_cache[cacheSet][location] = NULL;
 440     m_locked[cacheSet][location] = -1;
 441     m_tag_index.erase(address);
 442   }
 443 }
 444
 445 // Returns with the physical address of the conflicting cache line
 446 inline
 447 Address CacheMemory::cacheProbe(const Address& address) const
 448 {
 449   assert(address == line_address(address));
 450   assert(!cacheAvail(address));
 451
 452   Index cacheSet = addressToCacheSet(address);
 453   return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->m_Address;
 454 }
 455
 456 // looks an address up in the cache
 457 inline
 458 AbstractCacheEntry& CacheMemory::lookup(const Address& address)
 459 {
 460   assert(address == line_address(address));
 461   Index cacheSet = addressToCacheSet(address);
 462   int loc = findTagInSet(cacheSet, address);
 463   assert(loc != -1);
 464   return *m_cache[cacheSet][loc];
 465 }
 466
 467 // looks an address up in the cache
 468 inline
 469 const AbstractCacheEntry& CacheMemory::lookup(const Address& address) const
 470 {
 471   assert(address == line_address(address));
 472   Index cacheSet = addressToCacheSet(address);
 473   int loc = findTagInSet(cacheSet, address);
 474   assert(loc != -1);
 475   return *m_cache[cacheSet][loc];
 476 }
 477
 478 inline
 479 AccessPermission CacheMemory::getPermission(const Address& address) const
 480 {
 481   assert(address == line_address(address));
 482   return lookup(address).m_Permission;
 483 }
 484
 485 inline
 486 void CacheMemory::changePermission(const Address& address, AccessPermission new_perm)
 487 {
 488   assert(address == line_address(address));
 489   lookup(address).m_Permission = new_perm;
 490   Index cacheSet = addressToCacheSet(address);
 491   int loc = findTagInSet(cacheSet, address);
 492   m_locked[cacheSet][loc] = -1;
 493   assert(getPermission(address) == new_perm);
 494 }
 495
 496 // Sets the most recently used bit for a cache block
 497 inline
 498 void CacheMemory::setMRU(const Address& address)
 499 {
 500   Index cacheSet;
 501
 502   cacheSet = addressToCacheSet(address);
 503   m_replacementPolicy_ptr->touch(cacheSet,
 504                                  findTagInSet(cacheSet, address),
 505                                  g_eventQueue_ptr->getTime());
 506 }
 507
 508 inline
 509 void CacheMemory::profileMiss(const CacheMsg & msg)
 510 {
 511   m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(),
 512                                 msg.getSize(), msg.getPrefetch());
 513 }
 514
 515 inline
 516 void CacheMemory::recordCacheContents(CacheRecorder& tr) const
 517 {
 518   for (int i = 0; i < m_cache_num_sets; i++) {
 519     for (int j = 0; j < m_cache_assoc; j++) {
 520       AccessPermission perm = m_cache[i][j]->m_Permission;
 521       CacheRequestType request_type = CacheRequestType_NULL;
 522       if (perm == AccessPermission_Read_Only) {
 523         if (m_is_instruction_only_cache) {
 524           request_type = CacheRequestType_IFETCH;
 525         } else {
 526           request_type = CacheRequestType_LD;
 527         }
 528       } else if (perm == AccessPermission_Read_Write) {
 529         request_type = CacheRequestType_ST;
 530       }
 531
 532       if (request_type != CacheRequestType_NULL) {
 533         //        tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address,
 534         //                     Address(0), request_type, m_replacementPolicy_ptr->getLastAccess(i, j));
 535       }
 536     }
 537   }
 538 }
 539
 540 inline
 541 void CacheMemory::print(ostream& out) const
 542 {
 543   out << "Cache dump: " << m_cache_name << endl;
 544   for (int i = 0; i < m_cache_num_sets; i++) {
 545     for (int j = 0; j < m_cache_assoc; j++) {
 546       if (m_cache[i][j] != NULL) {
 547         out << "  Index: " << i
 548             << " way: " << j
 549             << " entry: " << *m_cache[i][j] << endl;
 550       } else {
 551         out << "  Index: " << i
 552             << " way: " << j
 553             << " entry: NULL" << endl;
 554       }
 555     }
 556   }
 557 }
 558
 559 inline
 560 void CacheMemory::printData(ostream& out) const
 561 {
 562   out << "printData() not supported" << endl;
 563 }
 564
 565 inline void CacheMemory::clearStats() const
 566 {
 567   m_profiler_ptr->clearStats();
 568 }
 569
 570 inline
 571 void CacheMemory::printStats(ostream& out) const
 572 {
 573   m_profiler_ptr->printStats(out);
 574 }
 575
 576 inline
 577 void CacheMemory::getMemoryValue(const Address& addr, char* value,
 578                                  unsigned int size_in_bytes ){
 579   AbstractCacheEntry& entry = lookup(line_address(addr));
 580   unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
 581   for(unsigned int i=0; i<size_in_bytes; ++i){
 582     value[i] = entry.getDataBlk().getByte(i + startByte);
 583   }
 584 }
 585
 586 inline
 587 void CacheMemory::setMemoryValue(const Address& addr, char* value,
 588                                  unsigned int size_in_bytes ){
 589   AbstractCacheEntry& entry = lookup(line_address(addr));
 590   unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
 591   assert(size_in_bytes > 0);
 592   for(unsigned int i=0; i<size_in_bytes; ++i){
 593     entry.getDataBlk().setByte(i + startByte, value[i]);
 594   }
 595
 596   //  entry = lookup(line_address(addr));
 597 }
 598
 599 inline
 600 void
 601 CacheMemory::setLocked(const Address& address, int context)
 602 {
 603   assert(address == line_address(address));
 604   Index cacheSet = addressToCacheSet(address);
 605   int loc = findTagInSet(cacheSet, address);
 606   assert(loc != -1);
 607   m_locked[cacheSet][loc] = context;
 608 }
 609
 610 inline
 611 void
 612 CacheMemory::clearLocked(const Address& address)
 613 {
 614   assert(address == line_address(address));
 615   Index cacheSet = addressToCacheSet(address);
 616   int loc = findTagInSet(cacheSet, address);
 617   assert(loc != -1);
 618   m_locked[cacheSet][loc] = -1;
 619 }
 620
 621 inline
 622 bool
 623 CacheMemory::isLocked(const Address& address, int context)
 624 {
 625   assert(address == line_address(address));
 626   Index cacheSet = addressToCacheSet(address);
 627   int loc = findTagInSet(cacheSet, address);
 628   assert(loc != -1);
 629   return m_locked[cacheSet][loc] == context;
 630 }
 631
 632 #endif //CACHEMEMORY_H
 633