src/mem/ruby/system/CacheMemory.hh

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * CacheMemory.hh
  31  *
  32  * Description:
  33  *
  34  * $Id: CacheMemory.hh,v 3.7 2004/06/18 20:15:15 beckmann Exp $
  35  *
  36  */
  37
  38 #ifndef CACHEMEMORY_H
  39 #define CACHEMEMORY_H
  40
  41 #include "sim/sim_object.hh"
  42 #include "params/RubyCache.hh"
  43
  44 #include "mem/ruby/common/Global.hh"
  45 #include "mem/protocol/AccessPermission.hh"
  46 #include "mem/ruby/common/Address.hh"
  47 #include "mem/ruby/recorder/CacheRecorder.hh"
  48 #include "mem/protocol/CacheRequestType.hh"
  49 #include "mem/gems_common/Vector.hh"
  50 #include "mem/ruby/common/DataBlock.hh"
  51 #include "mem/protocol/MachineType.hh"
  52 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
  53 #include "mem/ruby/system/PseudoLRUPolicy.hh"
  54 #include "mem/ruby/system/LRUPolicy.hh"
  55 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
  56 #include "mem/ruby/system/System.hh"
  57 #include "mem/ruby/slicc_interface/AbstractController.hh"
  58 #include "mem/ruby/profiler/CacheProfiler.hh"
  59 #include "mem/protocol/CacheMsg.hh"
  60 #include "base/hashmap.hh"
  61 #include <vector>
  62
  63 class CacheMemory : public SimObject {
  64 public:
  65
  66     typedef RubyCacheParams Params;
  67   // Constructors
  68   CacheMemory(const Params *p);
  69     // CacheMemory(const string & name);
  70   void init();
  71
  72   // Destructor
  73   ~CacheMemory();
  74
  75   // Public Methods
  76   void printConfig(ostream& out);
  77
  78   // perform a cache access and see if we hit or not.  Return true on a hit.
  79   bool tryCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
  80
  81   // similar to above, but doesn't require full access check
  82   bool testCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr);
  83
  84   // tests to see if an address is present in the cache
  85   bool isTagPresent(const Address& address) const;
  86
  87   // Returns true if there is:
  88   //   a) a tag match on this address or there is
  89   //   b) an unused line in the same cache "way"
  90   bool cacheAvail(const Address& address) const;
  91
  92   // find an unused entry and sets the tag appropriate for the address
  93   void allocate(const Address& address, AbstractCacheEntry* new_entry);
  94
  95   // Explicitly free up this address
  96   void deallocate(const Address& address);
  97
  98   // Returns with the physical address of the conflicting cache line
  99   Address cacheProbe(const Address& address) const;
 100
 101   // looks an address up in the cache
 102   AbstractCacheEntry& lookup(const Address& address);
 103   const AbstractCacheEntry& lookup(const Address& address) const;
 104
 105   // Get/Set permission of cache block
 106   AccessPermission getPermission(const Address& address) const;
 107   void changePermission(const Address& address, AccessPermission new_perm);
 108
 109   static int numberOfLastLevelCaches();
 110
 111   int getLatency() const { return m_latency; }
 112
 113   // Hook for checkpointing the contents of the cache
 114   void recordCacheContents(CacheRecorder& tr) const;
 115   void setAsInstructionCache(bool is_icache) { m_is_instruction_only_cache = is_icache; }
 116
 117   // Set this address to most recently used
 118   void setMRU(const Address& address);
 119
 120   void profileMiss(const CacheMsg & msg);
 121
 122   void getMemoryValue(const Address& addr, char* value,
 123                       unsigned int size_in_bytes );
 124   void setMemoryValue(const Address& addr, char* value,
 125                       unsigned int size_in_bytes );
 126
 127   void setLocked (const Address& addr, int context);
 128   void clearLocked (const Address& addr);
 129   bool isLocked (const Address& addr, int context);
 130   // Print cache contents
 131   void print(ostream& out) const;
 132   void printData(ostream& out) const;
 133
 134   void clearStats() const;
 135   void printStats(ostream& out) const;
 136
 137 private:
 138   // Private Methods
 139
 140   // convert a Address to its location in the cache
 141   Index addressToCacheSet(const Address& address) const;
 142
 143   // Given a cache tag: returns the index of the tag in a set.
 144   // returns -1 if the tag is not found.
 145   int findTagInSet(Index line, const Address& tag) const;
 146   int findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const;
 147
 148   // Private copy constructor and assignment operator
 149   CacheMemory(const CacheMemory& obj);
 150   CacheMemory& operator=(const CacheMemory& obj);
 151
 152 private:
 153   const string m_cache_name;
 154   int m_latency;
 155
 156   // Data Members (m_prefix)
 157   bool m_is_instruction_only_cache;
 158   bool m_is_data_only_cache;
 159
 160   // The first index is the # of cache lines.
 161   // The second index is the the amount associativity.
 162   m5::hash_map<Address, int> m_tag_index;
 163   Vector<Vector<AbstractCacheEntry*> > m_cache;
 164   Vector<Vector<int> > m_locked;
 165
 166   AbstractReplacementPolicy *m_replacementPolicy_ptr;
 167
 168   CacheProfiler* m_profiler_ptr;
 169
 170   int m_cache_size;
 171   string m_policy;
 172   int m_cache_num_sets;
 173   int m_cache_num_set_bits;
 174   int m_cache_assoc;
 175
 176   static Vector< CacheMemory* > m_all_caches;
 177
 178   static int m_num_last_level_caches;
 179   static MachineType m_last_level_machine_type;
 180
 181 };
 182
 183 #endif //CACHEMEMORY_H
 184