src/mem/ruby/system/DMASequencer.hh

   1
   2 #ifndef DMASEQUENCER_H
   3 #define DMASEQUENCER_H
   4
   5 #include <ostream>
   6 #include "mem/ruby/common/DataBlock.hh"
   7 #include "mem/ruby/system/RubyPort.hh"
   8
   9 struct DMARequest {
  10   uint64_t start_paddr;
  11   int len;
  12   bool write;
  13   int bytes_completed;
  14   int bytes_issued;
  15   uint8* data;
  16   int64_t id;
  17 };
  18
  19 class MessageBuffer;
  20 class AbstractController;
  21
  22 class DMASequencer :public RubyPort {
  23 public:
  24   DMASequencer(const string & name);
  25   void init(const vector<string> & argv);
  26   /* external interface */
  27   int64_t makeRequest(const RubyRequest & request);
  28   bool isReady(const RubyRequest & request, bool dont_set = false) { assert(0); return false;};
  29   //  void issueRequest(uint64_t paddr, uint8* data, int len, bool rw);
  30   bool busy() { return m_is_busy;}
  31
  32   /* SLICC callback */
  33   void dataCallback(const DataBlock & dblk);
  34   void ackCallback();
  35
  36   void printConfig(std::ostream & out);
  37
  38 private:
  39   void issueNext();
  40
  41 private:
  42   int m_version;
  43   AbstractController* m_controller;
  44   bool m_is_busy;
  45   uint64_t m_data_block_mask;
  46   DMARequest active_request;
  47   int num_active_requests;
  48   MessageBuffer* m_mandatory_q_ptr;
  49 };
  50
  51 #endif // DMACONTROLLER_H