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29 #ifndef __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__
30 #define __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__
32 #include "base/hashmap.hh"
33 #include "mem/protocol/AccessPermission.hh"
34 #include "mem/ruby/common/Address.hh"
35 #include "mem/ruby/common/Global.hh"
38 struct PerfectCacheLineState
40 PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
41 AccessPermission m_permission;
47 operator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj)
53 class PerfectCacheMemory
58 static void printConfig(std::ostream& out);
60 // perform a cache access and see if we hit or not. Return true
62 bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
64 // tests to see if an address is present in the cache
65 bool isTagPresent(const Address& address) const;
67 // Returns true if there is:
68 // a) a tag match on this address or there is
69 // b) an Invalid line in the same cache "way"
70 bool cacheAvail(const Address& address) const;
72 // find an Invalid entry and sets the tag appropriate for the address
73 void allocate(const Address& address);
75 void deallocate(const Address& address);
77 // Returns with the physical address of the conflicting cache line
78 Address cacheProbe(const Address& newAddress) const;
80 // looks an address up in the cache
81 ENTRY& lookup(const Address& address);
82 const ENTRY& lookup(const Address& address) const;
84 // Get/Set permission of cache block
85 AccessPermission getPermission(const Address& address) const;
86 void changePermission(const Address& address, AccessPermission new_perm);
88 // Print cache contents
89 void print(std::ostream& out) const;
92 // Private copy constructor and assignment operator
93 PerfectCacheMemory(const PerfectCacheMemory& obj);
94 PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
96 // Data Members (m_prefix)
97 m5::hash_map<Address, PerfectCacheLineState<ENTRY> > m_map;
100 template<class ENTRY>
102 operator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj)
109 template<class ENTRY>
111 PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
115 template<class ENTRY>
117 PerfectCacheMemory<ENTRY>::printConfig(std::ostream& out)
121 template<class ENTRY>
123 PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg,
124 bool& block_stc, ENTRY*& entry)
126 panic("not implemented");
130 // tests to see if an address is present in the cache
131 template<class ENTRY>
133 PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
135 return m_map.count(line_address(address)) > 0;
138 template<class ENTRY>
140 PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
145 // find an Invalid or already allocated entry and sets the tag
146 // appropriate for the address
147 template<class ENTRY>
149 PerfectCacheMemory<ENTRY>::allocate(const Address& address)
151 PerfectCacheLineState<ENTRY> line_state;
152 line_state.m_permission = AccessPermission_Busy;
153 line_state.m_entry = ENTRY();
154 m_map[line_address(address)] = line_state;
158 template<class ENTRY>
160 PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
162 m_map.erase(line_address(address));
165 // Returns with the physical address of the conflicting cache line
166 template<class ENTRY>
168 PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
170 panic("cacheProbe called in perfect cache");
174 // looks an address up in the cache
175 template<class ENTRY>
177 PerfectCacheMemory<ENTRY>::lookup(const Address& address)
179 return m_map[line_address(address)].m_entry;
182 // looks an address up in the cache
183 template<class ENTRY>
185 PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
187 return m_map[line_address(address)].m_entry;
190 template<class ENTRY>
191 inline AccessPermission
192 PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
194 return m_map[line_address(address)].m_permission;
197 template<class ENTRY>
199 PerfectCacheMemory<ENTRY>::changePermission(const Address& address,
200 AccessPermission new_perm)
202 Address line_address = address;
203 line_address.makeLineAddress();
204 PerfectCacheLineState<ENTRY>& line_state = m_map[line_address];
205 AccessPermission old_perm = line_state.m_permission;
206 line_state.m_permission = new_perm;
209 template<class ENTRY>
211 PerfectCacheMemory<ENTRY>::print(std::ostream& out) const
215 #endif // __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__