b04a6471701e984dc6ae6073c41d812c31218501
[gem5.git] / src / mem / ruby / system / PerfectCacheMemory.hh
1 /*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #ifndef __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__
30 #define __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__
31
32 #include "base/hashmap.hh"
33 #include "mem/protocol/AccessPermission.hh"
34 #include "mem/ruby/common/Address.hh"
35 #include "mem/ruby/common/Global.hh"
36
37 template<class ENTRY>
38 struct PerfectCacheLineState
39 {
40 PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
41 AccessPermission m_permission;
42 ENTRY m_entry;
43 };
44
45 template<class ENTRY>
46 inline std::ostream&
47 operator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj)
48 {
49 return out;
50 }
51
52 template<class ENTRY>
53 class PerfectCacheMemory
54 {
55 public:
56 PerfectCacheMemory();
57
58 static void printConfig(std::ostream& out);
59
60 // perform a cache access and see if we hit or not. Return true
61 // on a hit.
62 bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
63
64 // tests to see if an address is present in the cache
65 bool isTagPresent(const Address& address) const;
66
67 // Returns true if there is:
68 // a) a tag match on this address or there is
69 // b) an Invalid line in the same cache "way"
70 bool cacheAvail(const Address& address) const;
71
72 // find an Invalid entry and sets the tag appropriate for the address
73 void allocate(const Address& address);
74
75 void deallocate(const Address& address);
76
77 // Returns with the physical address of the conflicting cache line
78 Address cacheProbe(const Address& newAddress) const;
79
80 // looks an address up in the cache
81 ENTRY& lookup(const Address& address);
82 const ENTRY& lookup(const Address& address) const;
83
84 // Get/Set permission of cache block
85 AccessPermission getPermission(const Address& address) const;
86 void changePermission(const Address& address, AccessPermission new_perm);
87
88 // Print cache contents
89 void print(std::ostream& out) const;
90
91 private:
92 // Private copy constructor and assignment operator
93 PerfectCacheMemory(const PerfectCacheMemory& obj);
94 PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
95
96 // Data Members (m_prefix)
97 m5::hash_map<Address, PerfectCacheLineState<ENTRY> > m_map;
98 };
99
100 template<class ENTRY>
101 inline std::ostream&
102 operator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj)
103 {
104 obj.print(out);
105 out << std::flush;
106 return out;
107 }
108
109 template<class ENTRY>
110 inline
111 PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
112 {
113 }
114
115 template<class ENTRY>
116 inline void
117 PerfectCacheMemory<ENTRY>::printConfig(std::ostream& out)
118 {
119 }
120
121 template<class ENTRY>
122 inline bool
123 PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg,
124 bool& block_stc, ENTRY*& entry)
125 {
126 panic("not implemented");
127 return true;
128 }
129
130 // tests to see if an address is present in the cache
131 template<class ENTRY>
132 inline bool
133 PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
134 {
135 return m_map.count(line_address(address)) > 0;
136 }
137
138 template<class ENTRY>
139 inline bool
140 PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
141 {
142 return true;
143 }
144
145 // find an Invalid or already allocated entry and sets the tag
146 // appropriate for the address
147 template<class ENTRY>
148 inline void
149 PerfectCacheMemory<ENTRY>::allocate(const Address& address)
150 {
151 PerfectCacheLineState<ENTRY> line_state;
152 line_state.m_permission = AccessPermission_Busy;
153 line_state.m_entry = ENTRY();
154 m_map[line_address(address)] = line_state;
155 }
156
157 // deallocate entry
158 template<class ENTRY>
159 inline void
160 PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
161 {
162 m_map.erase(line_address(address));
163 }
164
165 // Returns with the physical address of the conflicting cache line
166 template<class ENTRY>
167 inline Address
168 PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
169 {
170 panic("cacheProbe called in perfect cache");
171 return newAddress;
172 }
173
174 // looks an address up in the cache
175 template<class ENTRY>
176 inline ENTRY&
177 PerfectCacheMemory<ENTRY>::lookup(const Address& address)
178 {
179 return m_map[line_address(address)].m_entry;
180 }
181
182 // looks an address up in the cache
183 template<class ENTRY>
184 inline const ENTRY&
185 PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
186 {
187 return m_map[line_address(address)].m_entry;
188 }
189
190 template<class ENTRY>
191 inline AccessPermission
192 PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
193 {
194 return m_map[line_address(address)].m_permission;
195 }
196
197 template<class ENTRY>
198 inline void
199 PerfectCacheMemory<ENTRY>::changePermission(const Address& address,
200 AccessPermission new_perm)
201 {
202 Address line_address = address;
203 line_address.makeLineAddress();
204 PerfectCacheLineState<ENTRY>& line_state = m_map[line_address];
205 AccessPermission old_perm = line_state.m_permission;
206 line_state.m_permission = new_perm;
207 }
208
209 template<class ENTRY>
210 inline void
211 PerfectCacheMemory<ENTRY>::print(std::ostream& out) const
212 {
213 }
214
215 #endif // __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__