src/mem/ruby/system/RubyPort.cc

   1 /*
   2  * Copyright (c) 2012-2013,2020 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
  15  * Copyright (c) 2011 Mark D. Hill and David A. Wood
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
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  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #include "mem/ruby/system/RubyPort.hh"
  43
  44 #include "cpu/testers/rubytest/RubyTester.hh"
  45 #include "debug/Config.hh"
  46 #include "debug/Drain.hh"
  47 #include "debug/Ruby.hh"
  48 #include "mem/ruby/protocol/AccessPermission.hh"
  49 #include "mem/ruby/slicc_interface/AbstractController.hh"
  50 #include "mem/simple_mem.hh"
  51 #include "sim/full_system.hh"
  52 #include "sim/system.hh"
  53
  54 RubyPort::RubyPort(const Params *p)
  55     : ClockedObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
  56       m_controller(NULL), m_mandatory_q_ptr(NULL),
  57       m_usingRubyTester(p->using_ruby_tester), system(p->system),
  58       pioMasterPort(csprintf("%s.pio-master-port", name()), this),
  59       pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
  60       memMasterPort(csprintf("%s.mem-master-port", name()), this),
  61       memSlavePort(csprintf("%s-mem-slave-port", name()), this,
  62                    p->ruby_system->getAccessBackingStore(), -1,
  63                    p->no_retry_on_stall),
  64       gotAddrRanges(p->port_master_connection_count),
  65       m_isCPUSequencer(p->is_cpu_sequencer)
  66 {
  67     assert(m_version != -1);
  68
  69     // create the slave ports based on the number of connected ports
  70     for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
  71         slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
  72             i), this, p->ruby_system->getAccessBackingStore(),
  73             i, p->no_retry_on_stall));
  74     }
  75
  76     // create the master ports based on the number of connected ports
  77     for (size_t i = 0; i < p->port_master_connection_count; ++i) {
  78         master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
  79             name(), i), this));
  80     }
  81 }
  82
  83 void
  84 RubyPort::init()
  85 {
  86     assert(m_controller != NULL);
  87     m_mandatory_q_ptr = m_controller->getMandatoryQueue();
  88 }
  89
  90 Port &
  91 RubyPort::getPort(const std::string &if_name, PortID idx)
  92 {
  93     if (if_name == "mem_master_port") {
  94         return memMasterPort;
  95     } else if (if_name == "pio_master_port") {
  96         return pioMasterPort;
  97     } else if (if_name == "mem_slave_port") {
  98         return memSlavePort;
  99     } else if (if_name == "pio_slave_port") {
 100         return pioSlavePort;
 101     } else if (if_name == "master") {
 102         // used by the x86 CPUs to connect the interrupt PIO and interrupt
 103         // slave port
 104         if (idx >= static_cast<PortID>(master_ports.size())) {
 105             panic("RubyPort::getPort master: unknown index %d\n", idx);
 106         }
 107
 108         return *master_ports[idx];
 109     } else if (if_name == "slave") {
 110         // used by the CPUs to connect the caches to the interconnect, and
 111         // for the x86 case also the interrupt master
 112         if (idx >= static_cast<PortID>(slave_ports.size())) {
 113             panic("RubyPort::getPort slave: unknown index %d\n", idx);
 114         }
 115
 116         return *slave_ports[idx];
 117     }
 118
 119     // pass it along to our super class
 120     return ClockedObject::getPort(if_name, idx);
 121 }
 122
 123 RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
 124                            RubyPort *_port)
 125     : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
 126       reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
 127 {
 128     DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
 129 }
 130
 131 RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
 132                            RubyPort *_port)
 133     : QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
 134 {
 135     DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
 136 }
 137
 138 RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
 139                            RubyPort *_port)
 140     : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
 141       reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
 142 {
 143     DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
 144 }
 145
 146 RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
 147                                      bool _access_backing_store, PortID id,
 148                                      bool _no_retry_on_stall)
 149     : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
 150       access_backing_store(_access_backing_store),
 151       no_retry_on_stall(_no_retry_on_stall)
 152 {
 153     DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
 154 }
 155
 156 bool
 157 RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
 158 {
 159     RubyPort *rp = static_cast<RubyPort *>(&owner);
 160     DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
 161
 162     // send next cycle
 163     rp->pioSlavePort.schedTimingResp(
 164             pkt, curTick() + rp->m_ruby_system->clockPeriod());
 165     return true;
 166 }
 167
 168 bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
 169 {
 170     // got a response from a device
 171     assert(pkt->isResponse());
 172     assert(!pkt->htmTransactionFailedInCache());
 173
 174     // First we must retrieve the request port from the sender State
 175     RubyPort::SenderState *senderState =
 176         safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
 177     MemSlavePort *port = senderState->port;
 178     assert(port != NULL);
 179     delete senderState;
 180
 181     // In FS mode, ruby memory will receive pio responses from devices
 182     // and it must forward these responses back to the particular CPU.
 183     DPRINTF(RubyPort,  "Pio response for address %#x, going to %s\n",
 184             pkt->getAddr(), port->name());
 185
 186     // attempt to send the response in the next cycle
 187     RubyPort *rp = static_cast<RubyPort *>(&owner);
 188     port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
 189
 190     return true;
 191 }
 192
 193 bool
 194 RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
 195 {
 196     RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 197
 198     for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
 199         AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
 200         for (auto it = l.begin(); it != l.end(); ++it) {
 201             if (it->contains(pkt->getAddr())) {
 202                 // generally it is not safe to assume success here as
 203                 // the port could be blocked
 204                 bool M5_VAR_USED success =
 205                     ruby_port->master_ports[i]->sendTimingReq(pkt);
 206                 assert(success);
 207                 return true;
 208             }
 209         }
 210     }
 211     panic("Should never reach here!\n");
 212 }
 213
 214 Tick
 215 RubyPort::PioSlavePort::recvAtomic(PacketPtr pkt)
 216 {
 217     RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 218     // Only atomic_noncaching mode supported!
 219     if (!ruby_port->system->bypassCaches()) {
 220         panic("Ruby supports atomic accesses only in noncaching mode\n");
 221     }
 222
 223     for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
 224         AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
 225         for (auto it = l.begin(); it != l.end(); ++it) {
 226             if (it->contains(pkt->getAddr())) {
 227                 return ruby_port->master_ports[i]->sendAtomic(pkt);
 228             }
 229         }
 230     }
 231     panic("Could not find address in Ruby PIO address ranges!\n");
 232 }
 233
 234 bool
 235 RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
 236 {
 237     DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
 238             pkt->getAddr(), id);
 239     RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 240
 241     if (pkt->cacheResponding())
 242         panic("RubyPort should never see request with the "
 243               "cacheResponding flag set\n");
 244
 245     // ruby doesn't support cache maintenance operations at the
 246     // moment, as a workaround, we respond right away
 247     if (pkt->req->isCacheMaintenance()) {
 248         warn_once("Cache maintenance operations are not supported in Ruby.\n");
 249         pkt->makeResponse();
 250         schedTimingResp(pkt, curTick());
 251         return true;
 252     }
 253     // Check for pio requests and directly send them to the dedicated
 254     // pio port.
 255     if (pkt->cmd != MemCmd::MemSyncReq) {
 256         if (!isPhysMemAddress(pkt)) {
 257             assert(!pkt->req->isHTMCmd());
 258             assert(ruby_port->memMasterPort.isConnected());
 259             DPRINTF(RubyPort, "Request address %#x assumed to be a "
 260                     "pio address\n", pkt->getAddr());
 261
 262             // Save the port in the sender state object to be used later to
 263             // route the response
 264             pkt->pushSenderState(new SenderState(this));
 265
 266             // send next cycle
 267             RubySystem *rs = ruby_port->m_ruby_system;
 268             ruby_port->memMasterPort.schedTimingReq(pkt,
 269                 curTick() + rs->clockPeriod());
 270             return true;
 271         }
 272     }
 273
 274     // Save the port in the sender state object to be used later to
 275     // route the response
 276     pkt->pushSenderState(new SenderState(this));
 277
 278     // Submit the ruby request
 279     RequestStatus requestStatus = ruby_port->makeRequest(pkt);
 280
 281     // If the request successfully issued then we should return true.
 282     // Otherwise, we need to tell the port to retry at a later point
 283     // and return false.
 284     if (requestStatus == RequestStatus_Issued) {
 285         DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(),
 286                 pkt->getAddr());
 287         return true;
 288     }
 289
 290     // pop off sender state as this request failed to issue
 291     SenderState *ss = safe_cast<SenderState *>(pkt->popSenderState());
 292     delete ss;
 293
 294     if (pkt->cmd != MemCmd::MemSyncReq) {
 295         DPRINTF(RubyPort,
 296                 "Request %s for address %#x did not issue because %s\n",
 297                 pkt->cmdString(), pkt->getAddr(),
 298                 RequestStatus_to_string(requestStatus));
 299     }
 300
 301     addToRetryList();
 302
 303     return false;
 304 }
 305
 306 Tick
 307 RubyPort::MemSlavePort::recvAtomic(PacketPtr pkt)
 308 {
 309     RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 310     // Only atomic_noncaching mode supported!
 311     if (!ruby_port->system->bypassCaches()) {
 312         panic("Ruby supports atomic accesses only in noncaching mode\n");
 313     }
 314
 315     // Check for pio requests and directly send them to the dedicated
 316     // pio port.
 317     if (pkt->cmd != MemCmd::MemSyncReq) {
 318         if (!isPhysMemAddress(pkt)) {
 319             assert(ruby_port->memMasterPort.isConnected());
 320             DPRINTF(RubyPort, "Request address %#x assumed to be a "
 321                     "pio address\n", pkt->getAddr());
 322
 323             // Save the port in the sender state object to be used later to
 324             // route the response
 325             pkt->pushSenderState(new SenderState(this));
 326
 327             // send next cycle
 328             Tick req_ticks = ruby_port->memMasterPort.sendAtomic(pkt);
 329             return ruby_port->ticksToCycles(req_ticks);
 330         }
 331
 332         assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
 333                RubySystem::getBlockSizeBytes());
 334     }
 335
 336     // Find appropriate directory for address
 337     // This assumes that protocols have a Directory machine,
 338     // which has its memPort hooked up to memory. This can
 339     // fail for some custom protocols.
 340     MachineID id = ruby_port->m_controller->mapAddressToMachine(
 341                     pkt->getAddr(), MachineType_Directory);
 342     RubySystem *rs = ruby_port->m_ruby_system;
 343     AbstractController *directory =
 344         rs->m_abstract_controls[id.getType()][id.getNum()];
 345     Tick latency = directory->recvAtomic(pkt);
 346     if (access_backing_store)
 347         rs->getPhysMem()->access(pkt);
 348     return latency;
 349 }
 350
 351 void
 352 RubyPort::MemSlavePort::addToRetryList()
 353 {
 354     RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 355
 356     //
 357     // Unless the requestor do not want retries (e.g., the Ruby tester),
 358     // record the stalled M5 port for later retry when the sequencer
 359     // becomes free.
 360     //
 361     if (!no_retry_on_stall && !ruby_port->onRetryList(this)) {
 362         ruby_port->addToRetryList(this);
 363     }
 364 }
 365
 366 void
 367 RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
 368 {
 369     DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
 370
 371     RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner);
 372     RubySystem *rs = rp->m_ruby_system;
 373
 374     // Check for pio requests and directly send them to the dedicated
 375     // pio port.
 376     if (!isPhysMemAddress(pkt)) {
 377         DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
 378         assert(rp->pioMasterPort.isConnected());
 379         rp->pioMasterPort.sendFunctional(pkt);
 380         return;
 381     }
 382
 383     assert(pkt->getAddr() + pkt->getSize() <=
 384            makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
 385
 386     if (access_backing_store) {
 387         // The attached physmem contains the official version of data.
 388         // The following command performs the real functional access.
 389         // This line should be removed once Ruby supplies the official version
 390         // of data.
 391         rs->getPhysMem()->functionalAccess(pkt);
 392     } else {
 393         bool accessSucceeded = false;
 394         bool needsResponse = pkt->needsResponse();
 395
 396         // Do the functional access on ruby memory
 397         if (pkt->isRead()) {
 398             accessSucceeded = rs->functionalRead(pkt);
 399         } else if (pkt->isWrite()) {
 400             accessSucceeded = rs->functionalWrite(pkt);
 401         } else {
 402             panic("Unsupported functional command %s\n", pkt->cmdString());
 403         }
 404
 405         // Unless the requester explicitly said otherwise, generate an error if
 406         // the functional request failed
 407         if (!accessSucceeded && !pkt->suppressFuncError()) {
 408             fatal("Ruby functional %s failed for address %#x\n",
 409                   pkt->isWrite() ? "write" : "read", pkt->getAddr());
 410         }
 411
 412         // turn packet around to go back to requester if response expected
 413         if (needsResponse) {
 414             // The pkt is already turned into a reponse if the directory
 415             // forwarded the request to the memory controller (see
 416             // AbstractController::functionalMemoryWrite and
 417             // AbstractMemory::functionalAccess)
 418             if (!pkt->isResponse())
 419                 pkt->makeResponse();
 420             pkt->setFunctionalResponseStatus(accessSucceeded);
 421         }
 422
 423         DPRINTF(RubyPort, "Functional access %s!\n",
 424                 accessSucceeded ? "successful":"failed");
 425     }
 426 }
 427
 428 void
 429 RubyPort::ruby_hit_callback(PacketPtr pkt)
 430 {
 431     DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
 432             pkt->getAddr());
 433
 434     // The packet was destined for memory and has not yet been turned
 435     // into a response
 436     assert(system->isMemAddr(pkt->getAddr()) || system->isDeviceMemAddr(pkt));
 437     assert(pkt->isRequest());
 438
 439     // First we must retrieve the request port from the sender State
 440     RubyPort::SenderState *senderState =
 441         safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
 442     MemSlavePort *port = senderState->port;
 443     assert(port != NULL);
 444     delete senderState;
 445
 446     port->hitCallback(pkt);
 447
 448     trySendRetries();
 449 }
 450
 451 void
 452 RubyPort::trySendRetries()
 453 {
 454     //
 455     // If we had to stall the MemSlavePorts, wake them up because the sequencer
 456     // likely has free resources now.
 457     //
 458     if (!retryList.empty()) {
 459         // Record the current list of ports to retry on a temporary list
 460         // before calling sendRetryReq on those ports. sendRetryReq will cause
 461         // an immediate retry, which may result in the ports being put back on
 462         // the list. Therefore we want to clear the retryList before calling
 463         // sendRetryReq.
 464         std::vector<MemSlavePort *> curRetryList(retryList);
 465
 466         retryList.clear();
 467
 468         for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
 469             DPRINTF(RubyPort,
 470                     "Sequencer may now be free. SendRetry to port %s\n",
 471                     (*i)->name());
 472             (*i)->sendRetryReq();
 473         }
 474     }
 475 }
 476
 477 void
 478 RubyPort::testDrainComplete()
 479 {
 480     //If we weren't able to drain before, we might be able to now.
 481     if (drainState() == DrainState::Draining) {
 482         unsigned int drainCount = outstandingCount();
 483         DPRINTF(Drain, "Drain count: %u\n", drainCount);
 484         if (drainCount == 0) {
 485             DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
 486             signalDrainDone();
 487         }
 488     }
 489 }
 490
 491 DrainState
 492 RubyPort::drain()
 493 {
 494     if (isDeadlockEventScheduled()) {
 495         descheduleDeadlockEvent();
 496     }
 497
 498     //
 499     // If the RubyPort is not empty, then it needs to clear all outstanding
 500     // requests before it should call signalDrainDone()
 501     //
 502     DPRINTF(Config, "outstanding count %d\n", outstandingCount());
 503     if (outstandingCount() > 0) {
 504         DPRINTF(Drain, "RubyPort not drained\n");
 505         return DrainState::Draining;
 506     } else {
 507         return DrainState::Drained;
 508     }
 509 }
 510
 511 void
 512 RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
 513 {
 514     bool needsResponse = pkt->needsResponse();
 515
 516     // Unless specified at configuraiton, all responses except failed SC
 517     // and Flush operations access M5 physical memory.
 518     bool accessPhysMem = access_backing_store;
 519
 520     if (pkt->isLLSC()) {
 521         if (pkt->isWrite()) {
 522             if (pkt->req->getExtraData() != 0) {
 523                 //
 524                 // Successful SC packets convert to normal writes
 525                 //
 526                 pkt->convertScToWrite();
 527             } else {
 528                 //
 529                 // Failed SC packets don't access physical memory and thus
 530                 // the RubyPort itself must convert it to a response.
 531                 //
 532                 accessPhysMem = false;
 533             }
 534         } else {
 535             //
 536             // All LL packets convert to normal loads so that M5 PhysMem does
 537             // not lock the blocks.
 538             //
 539             pkt->convertLlToRead();
 540         }
 541     }
 542
 543     // Flush, acquire, release requests don't access physical memory
 544     if (pkt->isFlush() || pkt->cmd == MemCmd::MemSyncReq) {
 545         accessPhysMem = false;
 546     }
 547
 548     if (pkt->req->isKernel()) {
 549         accessPhysMem = false;
 550         needsResponse = true;
 551     }
 552
 553     DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
 554
 555     RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 556     RubySystem *rs = ruby_port->m_ruby_system;
 557     if (accessPhysMem) {
 558         // We must check device memory first in case it overlaps with the
 559         // system memory range.
 560         if (ruby_port->system->isDeviceMemAddr(pkt)) {
 561             auto dmem = ruby_port->system->getDeviceMemory(pkt->masterId());
 562             dmem->access(pkt);
 563         } else if (ruby_port->system->isMemAddr(pkt->getAddr())) {
 564             rs->getPhysMem()->access(pkt);
 565         } else {
 566             panic("Packet is in neither device nor system memory!");
 567         }
 568     } else if (needsResponse) {
 569         pkt->makeResponse();
 570     }
 571
 572     // turn packet around to go back to requester if response expected
 573     if (needsResponse || pkt->isResponse()) {
 574         DPRINTF(RubyPort, "Sending packet back over port\n");
 575         // Send a response in the same cycle. There is no need to delay the
 576         // response because the response latency is already incurred in the
 577         // Ruby protocol.
 578         schedTimingResp(pkt, curTick());
 579     } else {
 580         delete pkt;
 581     }
 582
 583     DPRINTF(RubyPort, "Hit callback done!\n");
 584 }
 585
 586 AddrRangeList
 587 RubyPort::PioSlavePort::getAddrRanges() const
 588 {
 589     // at the moment the assumption is that the master does not care
 590     AddrRangeList ranges;
 591     RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 592
 593     for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
 594         ranges.splice(ranges.begin(),
 595                 ruby_port->master_ports[i]->getAddrRanges());
 596     }
 597     for (const auto M5_VAR_USED &r : ranges)
 598         DPRINTF(RubyPort, "%s\n", r.to_string());
 599     return ranges;
 600 }
 601
 602 bool
 603 RubyPort::MemSlavePort::isPhysMemAddress(PacketPtr pkt) const
 604 {
 605     RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 606     return ruby_port->system->isMemAddr(pkt->getAddr())
 607         || ruby_port->system->isDeviceMemAddr(pkt);
 608 }
 609
 610 void
 611 RubyPort::ruby_eviction_callback(Addr address)
 612 {
 613     DPRINTF(RubyPort, "Sending invalidations.\n");
 614     // Allocate the invalidate request and packet on the stack, as it is
 615     // assumed they will not be modified or deleted by receivers.
 616     // TODO: should this really be using funcMasterId?
 617     auto request = std::make_shared<Request>(
 618         address, RubySystem::getBlockSizeBytes(), 0,
 619         Request::funcMasterId);
 620
 621     // Use a single packet to signal all snooping ports of the invalidation.
 622     // This assumes that snooping ports do NOT modify the packet/request
 623     Packet pkt(request, MemCmd::InvalidateReq);
 624     for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
 625         // check if the connected master port is snooping
 626         if ((*p)->isSnooping()) {
 627             // send as a snoop request
 628             (*p)->sendTimingSnoopReq(&pkt);
 629         }
 630     }
 631 }
 632
 633 void
 634 RubyPort::PioMasterPort::recvRangeChange()
 635 {
 636     RubyPort &r = static_cast<RubyPort &>(owner);
 637     r.gotAddrRanges--;
 638     if (r.gotAddrRanges == 0 && FullSystem) {
 639         r.pioSlavePort.sendRangeChange();
 640     }
 641 }
 642
 643 int
 644 RubyPort::functionalWrite(Packet *func_pkt)
 645 {
 646     int num_written = 0;
 647     for (auto port : slave_ports) {
 648         if (port->trySatisfyFunctional(func_pkt)) {
 649             num_written += 1;
 650         }
 651     }
 652     return num_written;
 653 }