d14b3833ca4fdf80957631dae95ac6e1f96f9bdf
[gem5.git] / src / mem / ruby / system / RubySystem.hh
1 /*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Contains all of the various parts of the system we are simulating.
31 * Performs allocation, deallocation, and setup of all the major
32 * components of the system
33 */
34
35 #ifndef __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
36 #define __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
37
38 #include <unordered_map>
39
40 #include "base/callback.hh"
41 #include "base/output.hh"
42 #include "mem/packet.hh"
43 #include "mem/ruby/profiler/Profiler.hh"
44 #include "mem/ruby/slicc_interface/AbstractController.hh"
45 #include "mem/ruby/system/CacheRecorder.hh"
46 #include "params/RubySystem.hh"
47 #include "sim/clocked_object.hh"
48
49 class Network;
50 class AbstractController;
51
52 class RubySystem : public ClockedObject
53 {
54 public:
55 typedef RubySystemParams Params;
56 RubySystem(const Params *p);
57 ~RubySystem();
58 const Params *params() const { return (const Params *)_params; }
59
60 // config accessors
61 static int getRandomization() { return m_randomization; }
62 static uint32_t getBlockSizeBytes() { return m_block_size_bytes; }
63 static uint32_t getBlockSizeBits() { return m_block_size_bits; }
64 static uint32_t getMemorySizeBits() { return m_memory_size_bits; }
65 static bool getWarmupEnabled() { return m_warmup_enabled; }
66 static bool getCooldownEnabled() { return m_cooldown_enabled; }
67
68 SimpleMemory *getPhysMem() { return m_phys_mem; }
69 Cycles getStartCycle() { return m_start_cycle; }
70 bool getAccessBackingStore() { return m_access_backing_store; }
71
72 // Public Methods
73 Profiler*
74 getProfiler()
75 {
76 assert(m_profiler != NULL);
77 return m_profiler;
78 }
79
80 void regStats() override {
81 ClockedObject::regStats();
82 m_profiler->regStats(name());
83 }
84 void collateStats() { m_profiler->collateStats(); }
85 void resetStats() override;
86
87 void memWriteback() override;
88 void serialize(CheckpointOut &cp) const override;
89 void unserialize(CheckpointIn &cp) override;
90 void drainResume() override;
91 void process();
92 void init() override;
93 void startup() override;
94 bool functionalRead(Packet *ptr);
95 bool functionalWrite(Packet *ptr);
96
97 void registerNetwork(Network*);
98 void registerAbstractController(AbstractController*);
99 void registerMachineID(const MachineID& mach_id, Network* network);
100 void registerMasterIDs();
101
102 bool eventQueueEmpty() { return eventq->empty(); }
103 void enqueueRubyEvent(Tick tick)
104 {
105 auto e = new EventFunctionWrapper(
106 [this]{ processRubyEvent(); }, "RubyEvent");
107 schedule(e, tick);
108 }
109
110 private:
111 // Private copy constructor and assignment operator
112 RubySystem(const RubySystem& obj);
113 RubySystem& operator=(const RubySystem& obj);
114
115 void makeCacheRecorder(uint8_t *uncompressed_trace,
116 uint64_t cache_trace_size,
117 uint64_t block_size_bytes);
118
119 static void readCompressedTrace(std::string filename,
120 uint8_t *&raw_data,
121 uint64_t &uncompressed_trace_size);
122 static void writeCompressedTrace(uint8_t *raw_data, std::string file,
123 uint64_t uncompressed_trace_size);
124
125 void processRubyEvent();
126 private:
127 // configuration parameters
128 static bool m_randomization;
129 static uint32_t m_block_size_bytes;
130 static uint32_t m_block_size_bits;
131 static uint32_t m_memory_size_bits;
132
133 static bool m_warmup_enabled;
134 static unsigned m_systems_to_warmup;
135 static bool m_cooldown_enabled;
136 SimpleMemory *m_phys_mem;
137 const bool m_access_backing_store;
138
139 //std::vector<Network *> m_networks;
140 std::vector<std::unique_ptr<Network>> m_networks;
141 std::vector<AbstractController *> m_abs_cntrl_vec;
142 Cycles m_start_cycle;
143
144 std::unordered_map<MachineID, unsigned> machineToNetwork;
145 std::unordered_map<MasterID, unsigned> masterToNetwork;
146 std::unordered_map<unsigned, std::vector<AbstractController*>> netCntrls;
147
148 public:
149 Profiler* m_profiler;
150 CacheRecorder* m_cache_recorder;
151 std::vector<std::map<uint32_t, AbstractController *> > m_abstract_controls;
152 };
153
154 #endif //__MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__