3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include "mem/ruby/common/Global.hh"
31 #include "mem/ruby/system/Sequencer.hh"
32 #include "mem/ruby/system/System.hh"
33 #include "mem/protocol/Protocol.hh"
34 #include "mem/ruby/profiler/Profiler.hh"
35 #include "mem/ruby/system/CacheMemory.hh"
36 #include "mem/protocol/CacheMsg.hh"
37 #include "mem/ruby/recorder/Tracer.hh"
38 #include "mem/ruby/common/SubBlock.hh"
39 #include "mem/protocol/Protocol.hh"
40 #include "mem/gems_common/Map.hh"
41 #include "mem/ruby/buffers/MessageBuffer.hh"
42 #include "mem/ruby/slicc_interface/AbstractController.hh"
44 //Sequencer::Sequencer(int core_id, MessageBuffer* mandatory_q)
48 Sequencer::Sequencer(const string
& name
)
53 void Sequencer::init(const vector
<string
> & argv
)
55 m_deadlock_check_scheduled
= false;
56 m_outstanding_count
= 0;
58 m_max_outstanding_requests
= 0;
59 m_deadlock_threshold
= 0;
61 m_instCache_ptr
= NULL
;
62 m_dataCache_ptr
= NULL
;
64 m_servicing_atomic
= -1;
65 m_atomics_counter
= 0;
66 for (size_t i
=0; i
<argv
.size(); i
+=2) {
67 if ( argv
[i
] == "controller") {
68 m_controller
= RubySystem::getController(argv
[i
+1]); // args[i] = "L1Cache"
69 m_mandatory_q_ptr
= m_controller
->getMandatoryQueue();
70 } else if ( argv
[i
] == "icache")
71 m_instCache_ptr
= RubySystem::getCache(argv
[i
+1]);
72 else if ( argv
[i
] == "dcache")
73 m_dataCache_ptr
= RubySystem::getCache(argv
[i
+1]);
74 else if ( argv
[i
] == "version")
75 m_version
= atoi(argv
[i
+1].c_str());
76 else if ( argv
[i
] == "max_outstanding_requests")
77 m_max_outstanding_requests
= atoi(argv
[i
+1].c_str());
78 else if ( argv
[i
] == "deadlock_threshold")
79 m_deadlock_threshold
= atoi(argv
[i
+1].c_str());
81 cerr
<< "WARNING: Sequencer: Unkown configuration parameter: " << argv
[i
] << endl
;
85 assert(m_max_outstanding_requests
> 0);
86 assert(m_deadlock_threshold
> 0);
87 assert(m_version
> -1);
88 assert(m_instCache_ptr
!= NULL
);
89 assert(m_dataCache_ptr
!= NULL
);
90 assert(m_controller
!= NULL
);
93 Sequencer::~Sequencer() {
97 void Sequencer::wakeup() {
98 // Check for deadlock of any of the requests
99 Time current_time
= g_eventQueue_ptr
->getTime();
101 // Check across all outstanding requests
102 int total_outstanding
= 0;
104 Vector
<Address
> keys
= m_readRequestTable
.keys();
105 for (int i
=0; i
<keys
.size(); i
++) {
106 SequencerRequest
* request
= m_readRequestTable
.lookup(keys
[i
]);
107 if (current_time
- request
->issue_time
>= m_deadlock_threshold
) {
108 WARN_MSG("Possible Deadlock detected");
110 WARN_EXPR(m_version
);
111 WARN_EXPR(keys
.size());
112 WARN_EXPR(current_time
);
113 WARN_EXPR(request
->issue_time
);
114 WARN_EXPR(current_time
- request
->issue_time
);
115 ERROR_MSG("Aborting");
119 keys
= m_writeRequestTable
.keys();
120 for (int i
=0; i
<keys
.size(); i
++) {
121 SequencerRequest
* request
= m_writeRequestTable
.lookup(keys
[i
]);
122 if (current_time
- request
->issue_time
>= m_deadlock_threshold
) {
123 WARN_MSG("Possible Deadlock detected");
125 WARN_EXPR(m_version
);
126 WARN_EXPR(current_time
);
127 WARN_EXPR(request
->issue_time
);
128 WARN_EXPR(current_time
- request
->issue_time
);
129 WARN_EXPR(keys
.size());
130 ERROR_MSG("Aborting");
133 total_outstanding
+= m_writeRequestTable
.size() + m_readRequestTable
.size();
135 assert(m_outstanding_count
== total_outstanding
);
137 if (m_outstanding_count
> 0) { // If there are still outstanding requests, keep checking
138 g_eventQueue_ptr
->scheduleEvent(this, m_deadlock_threshold
);
140 m_deadlock_check_scheduled
= false;
144 void Sequencer::printProgress(ostream
& out
) const{
146 int total_demand = 0;
147 out << "Sequencer Stats Version " << m_version << endl;
148 out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
149 out << "---------------" << endl;
150 out << "outstanding requests" << endl;
152 Vector<Address> rkeys = m_readRequestTable.keys();
153 int read_size = rkeys.size();
154 out << "proc " << m_version << " Read Requests = " << read_size << endl;
155 // print the request table
156 for(int i=0; i < read_size; ++i){
157 SequencerRequest * request = m_readRequestTable.lookup(rkeys[i]);
158 out << "\tRequest[ " << i << " ] = " << request->type << " Address " << rkeys[i] << " Posted " << request->issue_time << " PF " << PrefetchBit_No << endl;
162 Vector<Address> wkeys = m_writeRequestTable.keys();
163 int write_size = wkeys.size();
164 out << "proc " << m_version << " Write Requests = " << write_size << endl;
165 // print the request table
166 for(int i=0; i < write_size; ++i){
167 CacheMsg & request = m_writeRequestTable.lookup(wkeys[i]);
168 out << "\tRequest[ " << i << " ] = " << request.getType() << " Address " << wkeys[i] << " Posted " << request.getTime() << " PF " << request.getPrefetch() << endl;
169 if( request.getPrefetch() == PrefetchBit_No ){
176 out << "Total Number Outstanding: " << m_outstanding_count << endl;
177 out << "Total Number Demand : " << total_demand << endl;
178 out << "Total Number Prefetches : " << m_outstanding_count - total_demand << endl;
184 void Sequencer::printConfig(ostream
& out
) const {
185 out
<< "Seqeuncer config: " << m_name
<< endl
;
186 out
<< " controller: " << m_controller
->getName() << endl
;
187 out
<< " version: " << m_version
<< endl
;
188 out
<< " max_outstanding_requests: " << m_max_outstanding_requests
<< endl
;
189 out
<< " deadlock_threshold: " << m_deadlock_threshold
<< endl
;
192 // Insert the request on the correct request table. Return true if
193 // the entry was already present.
194 bool Sequencer::insertRequest(SequencerRequest
* request
) {
195 int total_outstanding
= m_writeRequestTable
.size() + m_readRequestTable
.size();
197 assert(m_outstanding_count
== total_outstanding
);
199 // See if we should schedule a deadlock check
200 if (m_deadlock_check_scheduled
== false) {
201 g_eventQueue_ptr
->scheduleEvent(this, m_deadlock_threshold
);
202 m_deadlock_check_scheduled
= true;
205 Address
line_addr(request
->ruby_request
.paddr
);
206 line_addr
.makeLineAddress();
207 if ((request
->ruby_request
.type
== RubyRequestType_ST
) ||
208 (request
->ruby_request
.type
== RubyRequestType_RMW_Read
) ||
209 (request
->ruby_request
.type
== RubyRequestType_RMW_Write
) ||
210 (request
->ruby_request
.type
== RubyRequestType_Locked_Read
) ||
211 (request
->ruby_request
.type
== RubyRequestType_Locked_Write
)) {
212 if (m_writeRequestTable
.exist(line_addr
)) {
213 m_writeRequestTable
.lookup(line_addr
) = request
;
215 assert(0); // drh5: isn't this an error? do you lose the initial request?
217 m_writeRequestTable
.allocate(line_addr
);
218 m_writeRequestTable
.lookup(line_addr
) = request
;
219 m_outstanding_count
++;
221 if (m_readRequestTable
.exist(line_addr
)) {
222 m_readRequestTable
.lookup(line_addr
) = request
;
224 assert(0); // drh5: isn't this an error? do you lose the initial request?
226 m_readRequestTable
.allocate(line_addr
);
227 m_readRequestTable
.lookup(line_addr
) = request
;
228 m_outstanding_count
++;
231 g_system_ptr
->getProfiler()->sequencerRequests(m_outstanding_count
);
233 total_outstanding
= m_writeRequestTable
.size() + m_readRequestTable
.size();
234 assert(m_outstanding_count
== total_outstanding
);
239 void Sequencer::removeRequest(SequencerRequest
* srequest
) {
241 assert(m_outstanding_count
== m_writeRequestTable
.size() + m_readRequestTable
.size());
243 const RubyRequest
& ruby_request
= srequest
->ruby_request
;
244 Address
line_addr(ruby_request
.paddr
);
245 line_addr
.makeLineAddress();
246 if ((ruby_request
.type
== RubyRequestType_ST
) ||
247 (ruby_request
.type
== RubyRequestType_RMW_Read
) ||
248 (ruby_request
.type
== RubyRequestType_RMW_Write
) ||
249 (ruby_request
.type
== RubyRequestType_Locked_Read
) ||
250 (ruby_request
.type
== RubyRequestType_Locked_Write
)) {
251 m_writeRequestTable
.deallocate(line_addr
);
253 m_readRequestTable
.deallocate(line_addr
);
255 m_outstanding_count
--;
257 assert(m_outstanding_count
== m_writeRequestTable
.size() + m_readRequestTable
.size());
260 void Sequencer::writeCallback(const Address
& address
, DataBlock
& data
) {
262 assert(address
== line_address(address
));
263 assert(m_writeRequestTable
.exist(line_address(address
)));
265 SequencerRequest
* request
= m_writeRequestTable
.lookup(address
);
266 removeRequest(request
);
268 assert((request
->ruby_request
.type
== RubyRequestType_ST
) ||
269 (request
->ruby_request
.type
== RubyRequestType_RMW_Read
) ||
270 (request
->ruby_request
.type
== RubyRequestType_RMW_Write
) ||
271 (request
->ruby_request
.type
== RubyRequestType_Locked_Read
) ||
272 (request
->ruby_request
.type
== RubyRequestType_Locked_Write
));
273 // POLINA: the assumption is that atomics are only on data cache and not instruction cache
274 if (request
->ruby_request
.type
== RubyRequestType_Locked_Read
) {
275 m_dataCache_ptr
->setLocked(address
, m_version
);
277 else if (request
->ruby_request
.type
== RubyRequestType_RMW_Read
) {
278 m_controller
->set_atomic(address
);
280 else if (request
->ruby_request
.type
== RubyRequestType_RMW_Write
) {
281 m_controller
->clear_atomic();
284 hitCallback(request
, data
);
287 void Sequencer::readCallback(const Address
& address
, DataBlock
& data
) {
289 assert(address
== line_address(address
));
290 assert(m_readRequestTable
.exist(line_address(address
)));
292 SequencerRequest
* request
= m_readRequestTable
.lookup(address
);
293 removeRequest(request
);
295 assert((request
->ruby_request
.type
== RubyRequestType_LD
) ||
296 (request
->ruby_request
.type
== RubyRequestType_RMW_Read
) ||
297 (request
->ruby_request
.type
== RubyRequestType_IFETCH
));
299 hitCallback(request
, data
);
302 void Sequencer::hitCallback(SequencerRequest
* srequest
, DataBlock
& data
) {
303 const RubyRequest
& ruby_request
= srequest
->ruby_request
;
304 Address
request_address(ruby_request
.paddr
);
305 Address
request_line_address(ruby_request
.paddr
);
306 request_line_address
.makeLineAddress();
307 RubyRequestType type
= ruby_request
.type
;
308 Time issued_time
= srequest
->issue_time
;
310 // Set this cache entry to the most recently used
311 if (type
== RubyRequestType_IFETCH
) {
312 if (m_instCache_ptr
->isTagPresent(request_line_address
) )
313 m_instCache_ptr
->setMRU(request_line_address
);
315 if (m_dataCache_ptr
->isTagPresent(request_line_address
) )
316 m_dataCache_ptr
->setMRU(request_line_address
);
319 assert(g_eventQueue_ptr
->getTime() >= issued_time
);
320 Time miss_latency
= g_eventQueue_ptr
->getTime() - issued_time
;
322 // Profile the miss latency for all non-zero demand misses
323 if (miss_latency
!= 0) {
324 g_system_ptr
->getProfiler()->missLatency(miss_latency
, type
);
326 if (Debug::getProtocolTrace()) {
327 g_system_ptr
->getProfiler()->profileTransition("Seq", m_version
, Address(ruby_request
.paddr
),
328 "", "Done", "", int_to_string(miss_latency
)+" cycles");
332 if (request.getPrefetch() == PrefetchBit_Yes) {
333 return; // Ignore the prefetch
338 if (ruby_request
.data
!= NULL
) {
339 if ((type
== RubyRequestType_LD
) ||
340 (type
== RubyRequestType_IFETCH
) ||
341 (type
== RubyRequestType_RMW_Read
)) {
342 memcpy(ruby_request
.data
, data
.getData(request_address
.getOffset(), ruby_request
.len
), ruby_request
.len
);
344 data
.setData(ruby_request
.data
, request_address
.getOffset(), ruby_request
.len
);
348 m_hit_callback(srequest
->id
);
352 // Returns true if the sequencer already has a load or store outstanding
353 bool Sequencer::isReady(const RubyRequest
& request
) {
354 // POLINA: check if we are currently flushing the write buffer, if so Ruby is returned as not ready
355 // to simulate stalling of the front-end
356 // Do we stall all the sequencers? If it is atomic instruction - yes!
357 if (m_outstanding_count
>= m_max_outstanding_requests
) {
361 if( m_writeRequestTable
.exist(line_address(Address(request
.paddr
))) ||
362 m_readRequestTable
.exist(line_address(Address(request
.paddr
))) ){
363 //cout << "OUTSTANDING REQUEST EXISTS " << p << " VER " << m_version << endl;
364 //printProgress(cout);
368 if (m_servicing_atomic
!= -1 && m_servicing_atomic
!= (int)request
.proc_id
) {
369 assert(m_atomics_counter
> 0);
373 if (request
.type
== RubyRequestType_RMW_Read
) {
374 if (m_servicing_atomic
== -1) {
375 assert(m_atomics_counter
== 0);
376 m_servicing_atomic
= (int)request
.proc_id
;
379 assert(m_servicing_atomic
== (int)request
.proc_id
);
383 else if (request
.type
== RubyRequestType_RMW_Write
) {
384 assert(m_servicing_atomic
== (int)request
.proc_id
);
385 assert(m_atomics_counter
> 0);
387 if (m_atomics_counter
== 0) {
388 m_servicing_atomic
= -1;
396 bool Sequencer::empty() const {
397 return (m_writeRequestTable
.size() == 0) && (m_readRequestTable
.size() == 0);
401 int64_t Sequencer::makeRequest(const RubyRequest
& request
)
403 assert(Address(request
.paddr
).getOffset() + request
.len
<= RubySystem::getBlockSizeBytes());
404 if (isReady(request
)) {
405 int64_t id
= makeUniqueRequestID();
406 SequencerRequest
*srequest
= new SequencerRequest(request
, id
, g_eventQueue_ptr
->getTime());
407 bool found
= insertRequest(srequest
);
409 if (request
.type
== RubyRequestType_Locked_Write
) {
410 // NOTE: it is OK to check the locked flag here as the mandatory queue will be checked first
411 // ensuring that nothing comes between checking the flag and servicing the store
412 if (!m_dataCache_ptr
->isLocked(line_address(Address(request
.paddr
)), m_version
)) {
416 m_dataCache_ptr
->clearLocked(line_address(Address(request
.paddr
)));
419 if (request
.type
== RubyRequestType_RMW_Write
) {
420 m_controller
->started_writes();
422 issueRequest(request
);
424 // TODO: issue hardware prefetches here
432 void Sequencer::issueRequest(const RubyRequest
& request
) {
434 // TODO: get rid of CacheMsg, CacheRequestType, and AccessModeTYpe, & have SLICC use RubyRequest and subtypes natively
435 CacheRequestType ctype
;
436 switch(request
.type
) {
437 case RubyRequestType_IFETCH
:
438 ctype
= CacheRequestType_IFETCH
;
440 case RubyRequestType_LD
:
441 ctype
= CacheRequestType_LD
;
443 case RubyRequestType_ST
:
444 ctype
= CacheRequestType_ST
;
446 case RubyRequestType_Locked_Read
:
447 ctype
= CacheRequestType_ST
;
449 case RubyRequestType_Locked_Write
:
450 ctype
= CacheRequestType_ST
;
452 case RubyRequestType_RMW_Read
:
453 ctype
= CacheRequestType_ATOMIC
;
455 case RubyRequestType_RMW_Write
:
456 ctype
= CacheRequestType_ATOMIC
;
461 AccessModeType amtype
;
462 switch(request
.access_mode
){
463 case RubyAccessMode_User
:
464 amtype
= AccessModeType_UserMode
;
466 case RubyAccessMode_Supervisor
:
467 amtype
= AccessModeType_SupervisorMode
;
469 case RubyAccessMode_Device
:
470 amtype
= AccessModeType_UserMode
;
475 Address
line_addr(request
.paddr
);
476 line_addr
.makeLineAddress();
477 CacheMsg
msg(line_addr
, Address(request
.paddr
), ctype
, Address(request
.pc
), amtype
, request
.len
, PrefetchBit_No
, request
.proc_id
);
479 if (Debug::getProtocolTrace()) {
480 g_system_ptr
->getProfiler()->profileTransition("Seq", m_version
, Address(request
.paddr
),
481 "", "Begin", "", RubyRequestType_to_string(request
.type
));
484 if (g_system_ptr
->getTracer()->traceEnabled()) {
485 g_system_ptr
->getTracer()->traceRequest(m_name
, line_addr
, Address(request
.pc
),
486 request
.type
, g_eventQueue_ptr
->getTime());
489 Time latency
= 0; // initialzed to an null value
491 if (request
.type
== RubyRequestType_IFETCH
)
492 latency
= m_instCache_ptr
->getLatency();
494 latency
= m_dataCache_ptr
->getLatency();
496 // Send the message to the cache controller
500 m_mandatory_q_ptr
->enqueue(msg
, latency
);
503 bool Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
504 AccessModeType access_mode,
505 int size, DataBlock*& data_ptr) {
506 if (type == CacheRequestType_IFETCH) {
507 return m_instCache_ptr->tryCacheAccess(line_address(addr), type, data_ptr);
509 return m_dataCache_ptr->tryCacheAccess(line_address(addr), type, data_ptr);
514 void Sequencer::print(ostream
& out
) const {
515 out
<< "[Sequencer: " << m_version
516 << ", outstanding requests: " << m_outstanding_count
;
518 out
<< ", read request table: " << m_readRequestTable
519 << ", write request table: " << m_writeRequestTable
;
523 // this can be called from setState whenever coherence permissions are upgraded
524 // when invoked, coherence violations will be checked for the given block
525 void Sequencer::checkCoherence(const Address
& addr
) {
526 #ifdef CHECK_COHERENCE
527 g_system_ptr
->checkGlobalCoherenceInvariant(addr
);