src/mem/ruby/system/Sequencer.hh

   1 /*
   2  * Copyright (c) 2019-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
  42 #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
  43
  44 #include <iostream>
  45 #include <list>
  46 #include <unordered_map>
  47
  48 #include "mem/ruby/common/Address.hh"
  49 #include "mem/ruby/protocol/MachineType.hh"
  50 #include "mem/ruby/protocol/RubyRequestType.hh"
  51 #include "mem/ruby/protocol/SequencerRequestType.hh"
  52 #include "mem/ruby/structures/CacheMemory.hh"
  53 #include "mem/ruby/system/RubyPort.hh"
  54 #include "params/RubySequencer.hh"
  55
  56 struct SequencerRequest
  57 {
  58     PacketPtr pkt;
  59     RubyRequestType m_type;
  60     RubyRequestType m_second_type;
  61     Cycles issue_time;
  62     SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
  63                      RubyRequestType _m_second_type, Cycles _issue_time)
  64                 : pkt(_pkt), m_type(_m_type), m_second_type(_m_second_type),
  65                   issue_time(_issue_time)
  66     {}
  67
  68     bool functionalWrite(Packet *func_pkt) const
  69     {
  70         // Follow-up on RubyRequest::functionalWrite
  71         // This makes sure the hitCallback won't overrite the value we
  72         // expect to find
  73         assert(func_pkt->isWrite());
  74         return func_pkt->trySatisfyFunctional(pkt);
  75     }
  76 };
  77
  78 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
  79
  80 class Sequencer : public RubyPort
  81 {
  82   public:
  83     typedef RubySequencerParams Params;
  84     Sequencer(const Params *);
  85     ~Sequencer();
  86
  87     /**
  88      * Proxy function to writeCallback that first
  89      * invalidates the line address in the local monitor.
  90      */
  91     void writeCallbackScFail(Addr address,
  92                         DataBlock& data);
  93
  94     // Public Methods
  95     virtual void wakeup(); // Used only for deadlock detection
  96     void resetStats() override;
  97     void collateStats();
  98     void regStats() override;
  99
 100     void writeCallback(Addr address,
 101                        DataBlock& data,
 102                        const bool externalHit = false,
 103                        const MachineType mach = MachineType_NUM,
 104                        const Cycles initialRequestTime = Cycles(0),
 105                        const Cycles forwardRequestTime = Cycles(0),
 106                        const Cycles firstResponseTime = Cycles(0));
 107
 108     void readCallback(Addr address,
 109                       DataBlock& data,
 110                       const bool externalHit = false,
 111                       const MachineType mach = MachineType_NUM,
 112                       const Cycles initialRequestTime = Cycles(0),
 113                       const Cycles forwardRequestTime = Cycles(0),
 114                       const Cycles firstResponseTime = Cycles(0));
 115
 116     RequestStatus makeRequest(PacketPtr pkt) override;
 117     virtual bool empty() const;
 118     int outstandingCount() const override { return m_outstanding_count; }
 119
 120     bool isDeadlockEventScheduled() const override
 121     { return deadlockCheckEvent.scheduled(); }
 122
 123     void descheduleDeadlockEvent() override
 124     { deschedule(deadlockCheckEvent); }
 125
 126     virtual void print(std::ostream& out) const;
 127
 128     void markRemoved();
 129     void evictionCallback(Addr address);
 130     int coreId() const { return m_coreId; }
 131
 132     virtual int functionalWrite(Packet *func_pkt) override;
 133
 134     void recordRequestType(SequencerRequestType requestType);
 135     Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
 136
 137     Stats::Histogram& getLatencyHist() { return m_latencyHist; }
 138     Stats::Histogram& getTypeLatencyHist(uint32_t t)
 139     { return *m_typeLatencyHist[t]; }
 140
 141     Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; }
 142     Stats::Histogram& getHitTypeLatencyHist(uint32_t t)
 143     { return *m_hitTypeLatencyHist[t]; }
 144
 145     Stats::Histogram& getHitMachLatencyHist(uint32_t t)
 146     { return *m_hitMachLatencyHist[t]; }
 147
 148     Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
 149     { return *m_hitTypeMachLatencyHist[r][t]; }
 150
 151     Stats::Histogram& getMissLatencyHist()
 152     { return m_missLatencyHist; }
 153     Stats::Histogram& getMissTypeLatencyHist(uint32_t t)
 154     { return *m_missTypeLatencyHist[t]; }
 155
 156     Stats::Histogram& getMissMachLatencyHist(uint32_t t) const
 157     { return *m_missMachLatencyHist[t]; }
 158
 159     Stats::Histogram&
 160     getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
 161     { return *m_missTypeMachLatencyHist[r][t]; }
 162
 163     Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const
 164     { return *m_IssueToInitialDelayHist[t]; }
 165
 166     Stats::Histogram&
 167     getInitialToForwardDelayHist(const MachineType t) const
 168     { return *m_InitialToForwardDelayHist[t]; }
 169
 170     Stats::Histogram&
 171     getForwardRequestToFirstResponseHist(const MachineType t) const
 172     { return *m_ForwardToFirstResponseDelayHist[t]; }
 173
 174     Stats::Histogram&
 175     getFirstResponseToCompletionDelayHist(const MachineType t) const
 176     { return *m_FirstResponseToCompletionDelayHist[t]; }
 177
 178     Stats::Counter getIncompleteTimes(const MachineType t) const
 179     { return m_IncompleteTimes[t]; }
 180
 181   private:
 182     void issueRequest(PacketPtr pkt, RubyRequestType type);
 183
 184     void hitCallback(SequencerRequest* srequest, DataBlock& data,
 185                      bool llscSuccess,
 186                      const MachineType mach, const bool externalHit,
 187                      const Cycles initialRequestTime,
 188                      const Cycles forwardRequestTime,
 189                      const Cycles firstResponseTime);
 190
 191     void recordMissLatency(SequencerRequest* srequest, bool llscSuccess,
 192                            const MachineType respondingMach,
 193                            bool isExternalHit, Cycles initialRequestTime,
 194                            Cycles forwardRequestTime,
 195                            Cycles firstResponseTime);
 196
 197     // Private copy constructor and assignment operator
 198     Sequencer(const Sequencer& obj);
 199     Sequencer& operator=(const Sequencer& obj);
 200
 201   protected:
 202     // RequestTable contains both read and write requests, handles aliasing
 203     std::unordered_map<Addr, std::list<SequencerRequest>> m_RequestTable;
 204
 205     Cycles m_deadlock_threshold;
 206
 207     virtual RequestStatus insertRequest(PacketPtr pkt,
 208                                         RubyRequestType primary_type,
 209                                         RubyRequestType secondary_type);
 210
 211   private:
 212     int m_max_outstanding_requests;
 213
 214     CacheMemory* m_dataCache_ptr;
 215     CacheMemory* m_instCache_ptr;
 216
 217     // The cache access latency for top-level caches (L0/L1). These are
 218     // currently assessed at the beginning of each memory access through the
 219     // sequencer.
 220     // TODO: Migrate these latencies into top-level cache controllers.
 221     Cycles m_data_cache_hit_latency;
 222     Cycles m_inst_cache_hit_latency;
 223
 224     // Global outstanding request count, across all request tables
 225     int m_outstanding_count;
 226     bool m_deadlock_check_scheduled;
 227
 228     int m_coreId;
 229
 230     bool m_runningGarnetStandalone;
 231
 232     //! Histogram for number of outstanding requests per cycle.
 233     Stats::Histogram m_outstandReqHist;
 234
 235     //! Histogram for holding latency profile of all requests.
 236     Stats::Histogram m_latencyHist;
 237     std::vector<Stats::Histogram *> m_typeLatencyHist;
 238
 239     //! Histogram for holding latency profile of all requests that
 240     //! hit in the controller connected to this sequencer.
 241     Stats::Histogram m_hitLatencyHist;
 242     std::vector<Stats::Histogram *> m_hitTypeLatencyHist;
 243
 244     //! Histograms for profiling the latencies for requests that
 245     //! did not required external messages.
 246     std::vector<Stats::Histogram *> m_hitMachLatencyHist;
 247     std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist;
 248
 249     //! Histogram for holding latency profile of all requests that
 250     //! miss in the controller connected to this sequencer.
 251     Stats::Histogram m_missLatencyHist;
 252     std::vector<Stats::Histogram *> m_missTypeLatencyHist;
 253
 254     //! Histograms for profiling the latencies for requests that
 255     //! required external messages.
 256     std::vector<Stats::Histogram *> m_missMachLatencyHist;
 257     std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist;
 258
 259     //! Histograms for recording the breakdown of miss latency
 260     std::vector<Stats::Histogram *> m_IssueToInitialDelayHist;
 261     std::vector<Stats::Histogram *> m_InitialToForwardDelayHist;
 262     std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist;
 263     std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist;
 264     std::vector<Stats::Counter> m_IncompleteTimes;
 265
 266     EventFunctionWrapper deadlockCheckEvent;
 267
 268     // support for LL/SC
 269
 270     /**
 271      * Places the cache line address into the global monitor
 272      * tagged with this Sequencer object's version id.
 273      */
 274     void llscLoadLinked(const Addr);
 275
 276     /**
 277      * Removes the cache line address from the global monitor.
 278      * This is independent of this Sequencer object's version id.
 279      */
 280     void llscClearMonitor(const Addr);
 281
 282     /**
 283      * Searches for cache line address in the global monitor
 284      * tagged with this Sequencer object's version id.
 285      * If a match is found, the entry is is erased from
 286      * the global monitor.
 287      *
 288      * @return a boolean indicating if the line address was found.
 289      */
 290     bool llscStoreConditional(const Addr);
 291
 292   public:
 293     /**
 294      * Searches for cache line address in the global monitor
 295      * tagged with this Sequencer object's version id.
 296      *
 297      * @return a boolean indicating if the line address was found.
 298      */
 299     bool llscCheckMonitor(const Addr);
 300
 301
 302     /**
 303      * Removes all addresses from the local monitor.
 304      * This is independent of this Sequencer object's version id.
 305      */
 306     void llscClearLocalMonitor();
 307 };
 308
 309 inline std::ostream&
 310 operator<<(std::ostream& out, const Sequencer& obj)
 311 {
 312     obj.print(out);
 313     out << std::flush;
 314     return out;
 315 }
 316
 317 #endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__