src/mem/ruby/system/Sequencer.hh

   1 /*
   2  * Copyright (c) 2019 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
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  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
  42 #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
  43
  44 #include <iostream>
  45 #include <list>
  46 #include <unordered_map>
  47
  48 #include "mem/ruby/common/Address.hh"
  49 #include "mem/ruby/protocol/MachineType.hh"
  50 #include "mem/ruby/protocol/RubyRequestType.hh"
  51 #include "mem/ruby/protocol/SequencerRequestType.hh"
  52 #include "mem/ruby/structures/CacheMemory.hh"
  53 #include "mem/ruby/system/RubyPort.hh"
  54 #include "params/RubySequencer.hh"
  55
  56 struct SequencerRequest
  57 {
  58     PacketPtr pkt;
  59     RubyRequestType m_type;
  60     RubyRequestType m_second_type;
  61     Cycles issue_time;
  62     SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
  63                      RubyRequestType _m_second_type, Cycles _issue_time)
  64                 : pkt(_pkt), m_type(_m_type), m_second_type(_m_second_type),
  65                   issue_time(_issue_time)
  66     {}
  67
  68     bool functionalWrite(Packet *func_pkt) const
  69     {
  70         // Follow-up on RubyRequest::functionalWrite
  71         // This makes sure the hitCallback won't overrite the value we
  72         // expect to find
  73         assert(func_pkt->isWrite());
  74         return func_pkt->trySatisfyFunctional(pkt);
  75     }
  76 };
  77
  78 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
  79
  80 class Sequencer : public RubyPort
  81 {
  82   public:
  83     typedef RubySequencerParams Params;
  84     Sequencer(const Params *);
  85     ~Sequencer();
  86
  87     // Public Methods
  88     void wakeup(); // Used only for deadlock detection
  89     void resetStats() override;
  90     void collateStats();
  91     void regStats() override;
  92
  93     void writeCallback(Addr address,
  94                        DataBlock& data,
  95                        const bool externalHit = false,
  96                        const MachineType mach = MachineType_NUM,
  97                        const Cycles initialRequestTime = Cycles(0),
  98                        const Cycles forwardRequestTime = Cycles(0),
  99                        const Cycles firstResponseTime = Cycles(0));
 100
 101     void readCallback(Addr address,
 102                       DataBlock& data,
 103                       const bool externalHit = false,
 104                       const MachineType mach = MachineType_NUM,
 105                       const Cycles initialRequestTime = Cycles(0),
 106                       const Cycles forwardRequestTime = Cycles(0),
 107                       const Cycles firstResponseTime = Cycles(0));
 108
 109     RequestStatus makeRequest(PacketPtr pkt) override;
 110     bool empty() const;
 111     int outstandingCount() const override { return m_outstanding_count; }
 112
 113     bool isDeadlockEventScheduled() const override
 114     { return deadlockCheckEvent.scheduled(); }
 115
 116     void descheduleDeadlockEvent() override
 117     { deschedule(deadlockCheckEvent); }
 118
 119     void print(std::ostream& out) const;
 120     void checkCoherence(Addr address);
 121
 122     void markRemoved();
 123     void evictionCallback(Addr address);
 124     void invalidateSC(Addr address);
 125     int coreId() const { return m_coreId; }
 126
 127     virtual int functionalWrite(Packet *func_pkt) override;
 128
 129     void recordRequestType(SequencerRequestType requestType);
 130     Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
 131
 132     Stats::Histogram& getLatencyHist() { return m_latencyHist; }
 133     Stats::Histogram& getTypeLatencyHist(uint32_t t)
 134     { return *m_typeLatencyHist[t]; }
 135
 136     Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; }
 137     Stats::Histogram& getHitTypeLatencyHist(uint32_t t)
 138     { return *m_hitTypeLatencyHist[t]; }
 139
 140     Stats::Histogram& getHitMachLatencyHist(uint32_t t)
 141     { return *m_hitMachLatencyHist[t]; }
 142
 143     Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
 144     { return *m_hitTypeMachLatencyHist[r][t]; }
 145
 146     Stats::Histogram& getMissLatencyHist()
 147     { return m_missLatencyHist; }
 148     Stats::Histogram& getMissTypeLatencyHist(uint32_t t)
 149     { return *m_missTypeLatencyHist[t]; }
 150
 151     Stats::Histogram& getMissMachLatencyHist(uint32_t t) const
 152     { return *m_missMachLatencyHist[t]; }
 153
 154     Stats::Histogram&
 155     getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
 156     { return *m_missTypeMachLatencyHist[r][t]; }
 157
 158     Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const
 159     { return *m_IssueToInitialDelayHist[t]; }
 160
 161     Stats::Histogram&
 162     getInitialToForwardDelayHist(const MachineType t) const
 163     { return *m_InitialToForwardDelayHist[t]; }
 164
 165     Stats::Histogram&
 166     getForwardRequestToFirstResponseHist(const MachineType t) const
 167     { return *m_ForwardToFirstResponseDelayHist[t]; }
 168
 169     Stats::Histogram&
 170     getFirstResponseToCompletionDelayHist(const MachineType t) const
 171     { return *m_FirstResponseToCompletionDelayHist[t]; }
 172
 173     Stats::Counter getIncompleteTimes(const MachineType t) const
 174     { return m_IncompleteTimes[t]; }
 175
 176   private:
 177     void issueRequest(PacketPtr pkt, RubyRequestType type);
 178
 179     void hitCallback(SequencerRequest* srequest, DataBlock& data,
 180                      bool llscSuccess,
 181                      const MachineType mach, const bool externalHit,
 182                      const Cycles initialRequestTime,
 183                      const Cycles forwardRequestTime,
 184                      const Cycles firstResponseTime);
 185
 186     void recordMissLatency(SequencerRequest* srequest, bool llscSuccess,
 187                            const MachineType respondingMach,
 188                            bool isExternalHit, Cycles initialRequestTime,
 189                            Cycles forwardRequestTime,
 190                            Cycles firstResponseTime);
 191
 192     RequestStatus insertRequest(PacketPtr pkt, RubyRequestType primary_type,
 193                                 RubyRequestType secondary_type);
 194     bool handleLlsc(Addr address, SequencerRequest* request);
 195
 196     // Private copy constructor and assignment operator
 197     Sequencer(const Sequencer& obj);
 198     Sequencer& operator=(const Sequencer& obj);
 199
 200   private:
 201     int m_max_outstanding_requests;
 202     Cycles m_deadlock_threshold;
 203
 204     CacheMemory* m_dataCache_ptr;
 205     CacheMemory* m_instCache_ptr;
 206
 207     // The cache access latency for top-level caches (L0/L1). These are
 208     // currently assessed at the beginning of each memory access through the
 209     // sequencer.
 210     // TODO: Migrate these latencies into top-level cache controllers.
 211     Cycles m_data_cache_hit_latency;
 212     Cycles m_inst_cache_hit_latency;
 213
 214     // RequestTable contains both read and write requests, handles aliasing
 215     std::unordered_map<Addr, std::list<SequencerRequest>> m_RequestTable;
 216
 217     // Global outstanding request count, across all request tables
 218     int m_outstanding_count;
 219     bool m_deadlock_check_scheduled;
 220
 221     int m_coreId;
 222
 223     bool m_runningGarnetStandalone;
 224
 225     //! Histogram for number of outstanding requests per cycle.
 226     Stats::Histogram m_outstandReqHist;
 227
 228     //! Histogram for holding latency profile of all requests.
 229     Stats::Histogram m_latencyHist;
 230     std::vector<Stats::Histogram *> m_typeLatencyHist;
 231
 232     //! Histogram for holding latency profile of all requests that
 233     //! hit in the controller connected to this sequencer.
 234     Stats::Histogram m_hitLatencyHist;
 235     std::vector<Stats::Histogram *> m_hitTypeLatencyHist;
 236
 237     //! Histograms for profiling the latencies for requests that
 238     //! did not required external messages.
 239     std::vector<Stats::Histogram *> m_hitMachLatencyHist;
 240     std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist;
 241
 242     //! Histogram for holding latency profile of all requests that
 243     //! miss in the controller connected to this sequencer.
 244     Stats::Histogram m_missLatencyHist;
 245     std::vector<Stats::Histogram *> m_missTypeLatencyHist;
 246
 247     //! Histograms for profiling the latencies for requests that
 248     //! required external messages.
 249     std::vector<Stats::Histogram *> m_missMachLatencyHist;
 250     std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist;
 251
 252     //! Histograms for recording the breakdown of miss latency
 253     std::vector<Stats::Histogram *> m_IssueToInitialDelayHist;
 254     std::vector<Stats::Histogram *> m_InitialToForwardDelayHist;
 255     std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist;
 256     std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist;
 257     std::vector<Stats::Counter> m_IncompleteTimes;
 258
 259     EventFunctionWrapper deadlockCheckEvent;
 260 };
 261
 262 inline std::ostream&
 263 operator<<(std::ostream& out, const Sequencer& obj)
 264 {
 265     obj.print(out);
 266     out << std::flush;
 267     return out;
 268 }
 269
 270 #endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__