src/mem/ruby/system/Sequencer.hh

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
  30 #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
  31
  32 #include <iostream>
  33 #include <unordered_map>
  34
  35 #include "mem/protocol/MachineType.hh"
  36 #include "mem/protocol/RubyRequestType.hh"
  37 #include "mem/protocol/SequencerRequestType.hh"
  38 #include "mem/ruby/common/Address.hh"
  39 #include "mem/ruby/structures/CacheMemory.hh"
  40 #include "mem/ruby/system/RubyPort.hh"
  41 #include "params/RubySequencer.hh"
  42
  43 struct SequencerRequest
  44 {
  45     PacketPtr pkt;
  46     RubyRequestType m_type;
  47     Cycles issue_time;
  48
  49     SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
  50                      Cycles _issue_time)
  51         : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
  52     {}
  53 };
  54
  55 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
  56
  57 class Sequencer : public RubyPort
  58 {
  59   public:
  60     typedef RubySequencerParams Params;
  61     Sequencer(const Params *);
  62     ~Sequencer();
  63
  64     // Public Methods
  65     void wakeup(); // Used only for deadlock detection
  66     void resetStats();
  67     void collateStats();
  68     void regStats();
  69
  70     void writeCallback(Addr address,
  71                        DataBlock& data,
  72                        const bool externalHit = false,
  73                        const MachineType mach = MachineType_NUM,
  74                        const Cycles initialRequestTime = Cycles(0),
  75                        const Cycles forwardRequestTime = Cycles(0),
  76                        const Cycles firstResponseTime = Cycles(0));
  77
  78     void readCallback(Addr address,
  79                       DataBlock& data,
  80                       const bool externalHit = false,
  81                       const MachineType mach = MachineType_NUM,
  82                       const Cycles initialRequestTime = Cycles(0),
  83                       const Cycles forwardRequestTime = Cycles(0),
  84                       const Cycles firstResponseTime = Cycles(0));
  85
  86     RequestStatus makeRequest(PacketPtr pkt);
  87     bool empty() const;
  88     int outstandingCount() const { return m_outstanding_count; }
  89
  90     bool isDeadlockEventScheduled() const
  91     { return deadlockCheckEvent.scheduled(); }
  92
  93     void descheduleDeadlockEvent()
  94     { deschedule(deadlockCheckEvent); }
  95
  96     void print(std::ostream& out) const;
  97     void checkCoherence(Addr address);
  98
  99     void markRemoved();
 100     void evictionCallback(Addr address);
 101     void invalidateSC(Addr address);
 102     int coreId() const { return m_coreId; }
 103
 104     void recordRequestType(SequencerRequestType requestType);
 105     Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
 106
 107     Stats::Histogram& getLatencyHist() { return m_latencyHist; }
 108     Stats::Histogram& getTypeLatencyHist(uint32_t t)
 109     { return *m_typeLatencyHist[t]; }
 110
 111     Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; }
 112     Stats::Histogram& getHitTypeLatencyHist(uint32_t t)
 113     { return *m_hitTypeLatencyHist[t]; }
 114
 115     Stats::Histogram& getHitMachLatencyHist(uint32_t t)
 116     { return *m_hitMachLatencyHist[t]; }
 117
 118     Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
 119     { return *m_hitTypeMachLatencyHist[r][t]; }
 120
 121     Stats::Histogram& getMissLatencyHist()
 122     { return m_missLatencyHist; }
 123     Stats::Histogram& getMissTypeLatencyHist(uint32_t t)
 124     { return *m_missTypeLatencyHist[t]; }
 125
 126     Stats::Histogram& getMissMachLatencyHist(uint32_t t) const
 127     { return *m_missMachLatencyHist[t]; }
 128
 129     Stats::Histogram&
 130     getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
 131     { return *m_missTypeMachLatencyHist[r][t]; }
 132
 133     Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const
 134     { return *m_IssueToInitialDelayHist[t]; }
 135
 136     Stats::Histogram&
 137     getInitialToForwardDelayHist(const MachineType t) const
 138     { return *m_InitialToForwardDelayHist[t]; }
 139
 140     Stats::Histogram&
 141     getForwardRequestToFirstResponseHist(const MachineType t) const
 142     { return *m_ForwardToFirstResponseDelayHist[t]; }
 143
 144     Stats::Histogram&
 145     getFirstResponseToCompletionDelayHist(const MachineType t) const
 146     { return *m_FirstResponseToCompletionDelayHist[t]; }
 147
 148     Stats::Counter getIncompleteTimes(const MachineType t) const
 149     { return m_IncompleteTimes[t]; }
 150
 151   private:
 152     void issueRequest(PacketPtr pkt, RubyRequestType type);
 153
 154     void hitCallback(SequencerRequest* request, DataBlock& data,
 155                      bool llscSuccess,
 156                      const MachineType mach, const bool externalHit,
 157                      const Cycles initialRequestTime,
 158                      const Cycles forwardRequestTime,
 159                      const Cycles firstResponseTime);
 160
 161     void recordMissLatency(const Cycles t, const RubyRequestType type,
 162                            const MachineType respondingMach,
 163                            bool isExternalHit, Cycles issuedTime,
 164                            Cycles initialRequestTime,
 165                            Cycles forwardRequestTime, Cycles firstResponseTime,
 166                            Cycles completionTime);
 167
 168     RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
 169     bool handleLlsc(Addr address, SequencerRequest* request);
 170
 171     // Private copy constructor and assignment operator
 172     Sequencer(const Sequencer& obj);
 173     Sequencer& operator=(const Sequencer& obj);
 174
 175   private:
 176     int m_max_outstanding_requests;
 177     Cycles m_deadlock_threshold;
 178
 179     CacheMemory* m_dataCache_ptr;
 180     CacheMemory* m_instCache_ptr;
 181
 182     // The cache access latency for top-level caches (L0/L1). These are
 183     // currently assessed at the beginning of each memory access through the
 184     // sequencer.
 185     // TODO: Migrate these latencies into top-level cache controllers.
 186     Cycles m_data_cache_hit_latency;
 187     Cycles m_inst_cache_hit_latency;
 188
 189     typedef std::unordered_map<Addr, SequencerRequest*> RequestTable;
 190     RequestTable m_writeRequestTable;
 191     RequestTable m_readRequestTable;
 192     // Global outstanding request count, across all request tables
 193     int m_outstanding_count;
 194     bool m_deadlock_check_scheduled;
 195
 196     //! Counters for recording aliasing information.
 197     Stats::Scalar m_store_waiting_on_load;
 198     Stats::Scalar m_store_waiting_on_store;
 199     Stats::Scalar m_load_waiting_on_store;
 200     Stats::Scalar m_load_waiting_on_load;
 201
 202     int m_coreId;
 203
 204     bool m_runningGarnetStandalone;
 205
 206     //! Histogram for number of outstanding requests per cycle.
 207     Stats::Histogram m_outstandReqHist;
 208
 209     //! Histogram for holding latency profile of all requests.
 210     Stats::Histogram m_latencyHist;
 211     std::vector<Stats::Histogram *> m_typeLatencyHist;
 212
 213     //! Histogram for holding latency profile of all requests that
 214     //! hit in the controller connected to this sequencer.
 215     Stats::Histogram m_hitLatencyHist;
 216     std::vector<Stats::Histogram *> m_hitTypeLatencyHist;
 217
 218     //! Histograms for profiling the latencies for requests that
 219     //! did not required external messages.
 220     std::vector<Stats::Histogram *> m_hitMachLatencyHist;
 221     std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist;
 222
 223     //! Histogram for holding latency profile of all requests that
 224     //! miss in the controller connected to this sequencer.
 225     Stats::Histogram m_missLatencyHist;
 226     std::vector<Stats::Histogram *> m_missTypeLatencyHist;
 227
 228     //! Histograms for profiling the latencies for requests that
 229     //! required external messages.
 230     std::vector<Stats::Histogram *> m_missMachLatencyHist;
 231     std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist;
 232
 233     //! Histograms for recording the breakdown of miss latency
 234     std::vector<Stats::Histogram *> m_IssueToInitialDelayHist;
 235     std::vector<Stats::Histogram *> m_InitialToForwardDelayHist;
 236     std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist;
 237     std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist;
 238     std::vector<Stats::Counter> m_IncompleteTimes;
 239
 240     EventFunctionWrapper deadlockCheckEvent;
 241 };
 242
 243 inline std::ostream&
 244 operator<<(std::ostream& out, const Sequencer& obj)
 245 {
 246     obj.print(out);
 247     out << std::flush;
 248     return out;
 249 }
 250
 251 #endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__