src/mem/ruby/system/Sequencer.hh

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
  30 #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
  31
  32 #include <iostream>
  33
  34 #include "base/hashmap.hh"
  35 #include "mem/protocol/AccessModeType.hh"
  36 #include "mem/protocol/CacheRequestType.hh"
  37 #include "mem/protocol/GenericMachineType.hh"
  38 #include "mem/protocol/PrefetchBit.hh"
  39 #include "mem/ruby/common/Address.hh"
  40 #include "mem/ruby/common/Consumer.hh"
  41 #include "mem/ruby/common/Global.hh"
  42 #include "mem/ruby/system/RubyPort.hh"
  43
  44 class DataBlock;
  45 class CacheMsg;
  46 class MachineID;
  47 class CacheMemory;
  48
  49 class RubySequencerParams;
  50
  51 struct SequencerRequest
  52 {
  53     RubyRequest ruby_request;
  54     Time issue_time;
  55
  56     SequencerRequest(const RubyRequest & _ruby_request, Time _issue_time)
  57         : ruby_request(_ruby_request), issue_time(_issue_time)
  58     {}
  59 };
  60
  61 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
  62
  63 class Sequencer : public RubyPort, public Consumer
  64 {
  65   public:
  66     typedef RubySequencerParams Params;
  67     Sequencer(const Params *);
  68     ~Sequencer();
  69
  70     // Public Methods
  71     void wakeup(); // Used only for deadlock detection
  72
  73     void printConfig(std::ostream& out) const;
  74
  75     void printProgress(std::ostream& out) const;
  76
  77     void writeCallback(const Address& address, DataBlock& data);
  78
  79     void writeCallback(const Address& address,
  80                        GenericMachineType mach,
  81                        DataBlock& data);
  82
  83     void readCallback(const Address& address, DataBlock& data);
  84
  85     void readCallback(const Address& address,
  86                       GenericMachineType mach,
  87                       DataBlock& data);
  88
  89     RequestStatus makeRequest(const RubyRequest & request);
  90     RequestStatus getRequestStatus(const RubyRequest& request);
  91     bool empty() const;
  92
  93     void print(std::ostream& out) const;
  94     void printStats(std::ostream& out) const;
  95     void checkCoherence(const Address& address);
  96
  97     void markRemoved();
  98     void removeRequest(SequencerRequest* request);
  99
 100   private:
 101     bool tryCacheAccess(const Address& addr, CacheRequestType type,
 102                         const Address& pc, AccessModeType access_mode,
 103                         int size, DataBlock*& data_ptr);
 104     void issueRequest(const RubyRequest& request);
 105
 106     void hitCallback(SequencerRequest* request,
 107                      GenericMachineType mach,
 108                      DataBlock& data);
 109
 110     bool insertRequest(SequencerRequest* request);
 111
 112     void handleLlscWrites(const Address& address, SequencerRequest* request);
 113
 114     // Private copy constructor and assignment operator
 115     Sequencer(const Sequencer& obj);
 116     Sequencer& operator=(const Sequencer& obj);
 117
 118   private:
 119     int m_max_outstanding_requests;
 120     int m_deadlock_threshold;
 121
 122     CacheMemory* m_dataCache_ptr;
 123     CacheMemory* m_instCache_ptr;
 124
 125     typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
 126     RequestTable m_writeRequestTable;
 127     RequestTable m_readRequestTable;
 128     // Global outstanding request count, across all request tables
 129     int m_outstanding_count;
 130     bool m_deadlock_check_scheduled;
 131
 132     int m_store_waiting_on_load_cycles;
 133     int m_store_waiting_on_store_cycles;
 134     int m_load_waiting_on_store_cycles;
 135     int m_load_waiting_on_load_cycles;
 136
 137     bool m_usingRubyTester;
 138
 139     class SequencerWakeupEvent : public Event
 140     {
 141       private:
 142         Sequencer *m_sequencer_ptr;
 143
 144       public:
 145         SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {}
 146         void process() { m_sequencer_ptr->wakeup(); }
 147         const char *description() const { return "Sequencer deadlock check"; }
 148     };
 149
 150     SequencerWakeupEvent deadlockCheckEvent;
 151 };
 152
 153 inline std::ostream&
 154 operator<<(std::ostream& out, const Sequencer& obj)
 155 {
 156     obj.print(out);
 157     out << std::flush;
 158     return out;
 159 }
 160
 161 #endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
 162