3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * Description: Contains all of the various parts of the system we are
34 * simulating. Performs allocation, deallocation, and setup of all
35 * the major components of the system
44 #include "mem/ruby/system/RubyPort.hh"
45 #include "mem/ruby/common/Global.hh"
46 #include "mem/gems_common/Vector.hh"
47 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
57 class AbstractController;
60 class DirectoryMemory;
65 * This defines the number of longs (32-bits on 32 bit machines,
66 * 64-bit on 64-bit AMD machines) to use to hold the set...
67 * the default is 4, allowing 128 or 256 different members
70 * This should never need to be changed for correctness reasons,
71 * though increasing it will increase performance for larger
72 * set sizes at the cost of a (much) larger memory footprint
75 const int NUMBER_WORDS_PER_SET = 4;
82 RubyObjConf(string _type, string _name, vector<string> _argv)
83 : type(_type), name(_name), argv(_argv)
89 static RubySystem* create(const vector <RubyObjConf> & sys_conf);
94 static int getRandomSeed() { return m_random_seed; }
95 static int getRandomization() { return m_randomization; }
96 static int getTechNm() { return m_tech_nm; }
97 static int getFreqMhz() { return m_freq_mhz; }
98 static int getBlockSizeBytes() { return m_block_size_bytes; }
99 static int getBlockSizeBits() { return m_block_size_bits; }
100 static uint64 getMemorySizeBytes() { return m_memory_size_bytes; }
101 static int getMemorySizeBits() { return m_memory_size_bits; }
104 static RubyPort* getPortOnly(const string & name) {
105 assert(m_ports.count(name) == 1); return m_ports[name]; }
106 static RubyPort* getPort(const string & name, void (*hit_callback)(int64_t)) {
107 if (m_ports.count(name) != 1){
108 cerr << "Port " << name << " has " << m_ports.count(name) << " instances" << endl;
110 assert(m_ports.count(name) == 1); m_ports[name]->registerHitCallback(hit_callback); return m_ports[name]; }
111 static Network* getNetwork() { assert(m_network_ptr != NULL); return m_network_ptr; }
112 static Topology* getTopology(const string & name) { assert(m_topologies.count(name) == 1); return m_topologies[name]; }
113 static CacheMemory* getCache(const string & name) { assert(m_caches.count(name) == 1); return m_caches[name]; }
114 static DirectoryMemory* getDirectory(const string & name) { assert(m_directories.count(name) == 1); return m_directories[name]; }
115 static MemoryControl* getMemoryControl(const string & name) { assert(m_memorycontrols.count(name) == 1); return m_memorycontrols[name]; }
116 static Sequencer* getSequencer(const string & name) { assert(m_sequencers.count(name) == 1); return m_sequencers[name]; }
117 static DMASequencer* getDMASequencer(const string & name) { assert(m_dma_sequencers.count(name) == 1); return m_dma_sequencers[name]; }
118 static AbstractController* getController(const string & name) { assert(m_controllers.count(name) == 1); return m_controllers[name]; }
120 static RubyEventQueue* getEventQueue() { return g_eventQueue_ptr; }
122 static int getNumberOfDirectories() { return m_directories.size(); }
123 static int getNumberOfSequencers() { return m_sequencers.size(); }
125 Profiler* getProfiler() {assert(m_profiler_ptr != NULL); return m_profiler_ptr; }
126 static Tracer* getTracer() { assert(m_tracer_ptr != NULL); return m_tracer_ptr; }
127 static MemoryVector* getMemoryVector() { assert(m_mem_vec_ptr != NULL); return m_mem_vec_ptr;}
129 void recordCacheContents(CacheRecorder& tr) const;
130 static void printConfig(ostream& out);
131 static void printStats(ostream& out);
132 void clearStats() const;
134 uint64 getInstructionCount(int thread) { return 1; }
135 static uint64 getCycleCount(int thread) { return g_eventQueue_ptr->getTime(); }
137 void print(ostream& out) const;
139 #ifdef CHECK_COHERENCE
140 void checkGlobalCoherenceInvariant(const Address& addr);
146 RubySystem(const vector <RubyObjConf> & cfg_file);
148 // Private copy constructor and assignment operator
149 RubySystem(const RubySystem& obj);
150 RubySystem& operator=(const RubySystem& obj);
152 void init(const vector<string> & argv);
154 static void printSystemConfig(ostream& out);
157 // configuration parameters
158 static int m_random_seed;
159 static bool m_randomization;
160 static int m_tech_nm;
161 static int m_freq_mhz;
162 static int m_block_size_bytes;
163 static int m_block_size_bits;
164 static uint64 m_memory_size_bytes;
165 static int m_memory_size_bits;
167 // Data Members (m_ prefix)
168 static Network* m_network_ptr;
169 static map< string, Topology* > m_topologies;
170 static map< string, RubyPort* > m_ports;
171 static map< string, CacheMemory* > m_caches;
172 static map< string, DirectoryMemory* > m_directories;
173 static map< string, Sequencer* > m_sequencers;
174 static map< string, DMASequencer* > m_dma_sequencers;
175 static map< string, AbstractController* > m_controllers;
176 static map< string, MemoryControl* > m_memorycontrols;
179 //static map< string, Tracer* > m_tracers;
181 static Profiler* m_profiler_ptr;
182 static Tracer* m_tracer_ptr;
183 static MemoryVector* m_mem_vec_ptr;
186 // Output operator declaration
187 ostream& operator<<(ostream& out, const RubySystem& obj);
189 // ******************* Definitions *******************
191 // Output operator definition
193 ostream& operator<<(ostream& out, const RubySystem& obj)