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37 * Authors: Andreas Hansson
43 * SimpleDRAM declaration
46 #ifndef __MEM_SIMPLE_DRAM_HH__
47 #define __MEM_SIMPLE_DRAM_HH__
49 #include "base/statistics.hh"
50 #include "enums/AddrMap.hh"
51 #include "enums/MemSched.hh"
52 #include "enums/PageManage.hh"
53 #include "mem/abstract_mem.hh"
54 #include "mem/qport.hh"
55 #include "params/SimpleDRAM.hh"
56 #include "sim/eventq.hh"
59 * The simple DRAM is a basic single-channel memory controller aiming
60 * to mimic a high-level DRAM controller and the most important timing
61 * constraints associated with the DRAM. The focus is really on
62 * modelling the impact on the system rather than the DRAM itself,
63 * hence the focus is on the controller model and not on the
64 * memory. By adhering to the correct timing constraints, ultimately
65 * there is no need for a memory model in addition to the controller
68 * As a basic design principle, this controller is not cycle callable,
69 * but instead uses events to decide when new decisions can be made,
70 * when resources become available, when things are to be considered
71 * done, and when to send things back. Through these simple
72 * principles, we achieve a performant model that is not
73 * cycle-accurate, but enables us to evaluate the system impact of a
74 * wide range of memory technologies, and also collect statistics
75 * about the use of the memory.
77 class SimpleDRAM : public AbstractMemory
82 // For now, make use of a queued slave port to avoid dealing with
83 // flow control for the responses being sent back
84 class MemoryPort : public QueuedSlavePort
87 SlavePacketQueue queue;
92 MemoryPort(const std::string& name, SimpleDRAM& _memory);
96 Tick recvAtomic(PacketPtr pkt);
98 void recvFunctional(PacketPtr pkt);
100 bool recvTimingReq(PacketPtr);
102 virtual AddrRangeList getAddrRanges() const;
107 * Our incoming port, for a multi-ported controller add a crossbar
113 * Remember if we have to retry a request when available.
119 * Remember that a row buffer hit occured
124 * Use this flag to shutoff reads, i.e. do not schedule any reads
125 * beyond those already done so that we can turn the bus around
126 * and do a few writes, or refresh, or whatever
131 * A basic class to track the bank state indirectly via
132 * times "freeAt" and "tRASDoneAt" and what page is currently open
139 static const uint32_t INVALID_ROW = -1;
146 Bank() : openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0)
151 * A DRAM packet stores packets along with the timestamp of when
152 * the packet entered the queue, and also the decoded address.
158 /** When did request enter the controller */
159 const Tick entryTime;
161 /** When will request leave the controller */
164 /** This comes from the outside world */
167 /** Will be populated by address decoder */
174 DRAMPacket(PacketPtr _pkt, uint8_t _rank,
175 uint16_t _bank, uint16_t _row, Addr _addr, Bank& _bank_ref)
176 : entryTime(curTick()), readyTime(curTick()),
177 pkt(_pkt), rank(_rank), bank(_bank), row(_row), addr(_addr),
184 * Bunch of things requires to setup "events" in gem5
185 * When event "writeEvent" occurs for example, the method
186 * processWriteEvent is called; no parameters are allowed
189 void processWriteEvent();
190 EventWrapper<SimpleDRAM, &SimpleDRAM::processWriteEvent> writeEvent;
192 void processRespondEvent();
193 EventWrapper<SimpleDRAM, &SimpleDRAM::processRespondEvent> respondEvent;
195 void processRefreshEvent();
196 EventWrapper<SimpleDRAM, &SimpleDRAM::processRefreshEvent> refreshEvent;
198 void processNextReqEvent();
199 EventWrapper<SimpleDRAM,&SimpleDRAM::processNextReqEvent> nextReqEvent;
203 * Check if the read queue has room for more entries
205 * @return true if read queue is full, false otherwise
207 bool readQueueFull() const;
210 * Check if the write queue has room for more entries
212 * @return true if write queue is full, false otherwise
214 bool writeQueueFull() const;
217 * When a new read comes in, first check if the write q has a
218 * pending request to the same address.\ If not, decode the
219 * address to populate rank/bank/row, create a "dram_pkt", and
220 * push it to the back of the read queue.\ If this is the only
221 * read request in the system, schedule an event to start
224 * @param pkt The request packet from the outside world
226 void addToReadQueue(PacketPtr pkt);
229 * Decode the incoming pkt, create a dram_pkt and push to the
230 * back of the write queue. \If the write q length is more than
231 * the threshold specified by the user, ie the queue is beginning
232 * to get full, stop reads, and start draining writes.
234 * @param pkt The request packet from the outside world
236 void addToWriteQueue(PacketPtr pkt);
239 * Actually do the DRAM access - figure out the latency it
240 * will take to service the req based on bank state, channel state etc
241 * and then update those states to account for this request.\ Based
242 * on this, update the packet's "readyTime" and move it to the
243 * response q from where it will eventually go back to the outside
246 * @param pkt The DRAM packet created from the outside world pkt
248 void doDRAMAccess(DRAMPacket* dram_pkt);
251 * Check when the channel is free to turnaround, add turnaround
252 * delay and schedule a whole bunch of writes.
254 void triggerWrites();
257 * When a packet reaches its "readyTime" in the response Q,
258 * use the "access()" method in AbstractMemory to actually
259 * create the response packet, and send it back to the outside
262 * @param pkt The packet from the outside world
264 void accessAndRespond(PacketPtr pkt);
267 * Address decoder to figure out physical mapping onto ranks,
270 * @param pkt The packet from the outside world
271 * @return A DRAMPacket pointer with the decoded information
273 DRAMPacket* decodeAddr(PacketPtr pkt);
276 * The memory schduler/arbiter - picks which request needs to
277 * go next, based on the specified policy such as fcfs or frfcfs
278 * and moves it to the head of the read queue
280 * @return True if a request was chosen, False if Q is empty
282 bool chooseNextReq();
285 * Calls chooseNextReq() to pick the right request, then calls
286 * doDRAMAccess on that request in order to actually service
289 void scheduleNextReq();
292 *Looks at the state of the banks, channels, row buffer hits etc
293 * to estimate how long a request will take to complete.
295 * @param dram_pkt The request for which we want to estimate latency
296 * @param inTime The tick at which you want to probe the memory
298 * @return A pair of ticks, one indicating how many ticks *after*
299 * inTime the request require, and the other indicating how
300 * much of that was just the bank access time, ignoring the
301 * ticks spent simply waiting for resources to become free
303 std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime);
306 * Move the request at the head of the read queue to the response
307 * queue, sorting by readyTime.\ If it is the only packet in the
308 * response queue, schedule a respond event to send it back to the
314 * Scheduling policy within the write Q
316 void chooseNextWrite();
319 * Looking at all banks, determine the moment in time when they
322 * @return The tick when all banks are free
324 Tick maxBankFreeAt() const;
326 void printParams() const;
327 void printQs() const;
330 * The controller's main read and write queues
332 std::list<DRAMPacket*> dramReadQueue;
333 std::list<DRAMPacket*> dramWriteQueue;
336 * Response queue where read packets wait after we're done working
337 * with them, but it's not time to send the response yet.\ It is
338 * seperate mostly to keep the code clean and help with gem5 events,
339 * but for all logical purposes such as sizing the read queue, this
340 * and the main read queue need to be added together.
342 std::list<DRAMPacket*> dramRespQueue;
344 /** If we need to drain, keep the drain event around until we're done
350 * Multi-dimensional vector of banks, first dimension is ranks,
353 std::vector<std::vector<Bank> > banks;
356 * The following are basic design parameters of the memory
357 * controller, and are initialized based on parameter values. The
358 * bytesPerCacheLine is based on the neighbouring port and thus
359 * determined outside the constructor. Similarly, the rowsPerBank
360 * is determined based on the capacity, number of ranks and banks,
361 * the cache line size, and the row buffer size.
363 uint32_t bytesPerCacheLine;
364 const uint32_t linesPerRowBuffer;
365 const uint32_t ranksPerChannel;
366 const uint32_t banksPerRank;
367 uint32_t rowsPerBank;
368 const uint32_t readBufferSize;
369 const uint32_t writeBufferSize;
370 const double writeThresholdPerc;
371 uint32_t writeThreshold;
374 * Basic memory timing parameters initialized based on parameter
386 * Memory controller configuration initialized based on parameter
389 Enums::MemSched memSchedPolicy;
390 Enums::AddrMap addrMapping;
391 Enums::PageManage pageMgmt;
394 * Till when has the main data bus been spoken for already?
403 // All statistics that the model needs to capture
404 Stats::Scalar readReqs;
405 Stats::Scalar writeReqs;
406 Stats::Scalar cpuReqs;
407 Stats::Scalar bytesRead;
408 Stats::Scalar bytesWritten;
409 Stats::Scalar bytesConsumedRd;
410 Stats::Scalar bytesConsumedWr;
411 Stats::Scalar servicedByWrQ;
412 Stats::Scalar neitherReadNorWrite;
413 Stats::Vector perBankRdReqs;
414 Stats::Vector perBankWrReqs;
415 Stats::Scalar numRdRetry;
416 Stats::Scalar numWrRetry;
417 Stats::Scalar totGap;
418 Stats::Vector readPktSize;
419 Stats::Vector writePktSize;
420 Stats::Vector neitherPktSize;
421 Stats::Vector rdQLenPdf;
422 Stats::Vector wrQLenPdf;
425 // Latencies summed over all requests
426 Stats::Scalar totQLat;
427 Stats::Scalar totMemAccLat;
428 Stats::Scalar totBusLat;
429 Stats::Scalar totBankLat;
431 // Average latencies per request
432 Stats::Formula avgQLat;
433 Stats::Formula avgBankLat;
434 Stats::Formula avgBusLat;
435 Stats::Formula avgMemAccLat;
438 Stats::Formula avgRdBW;
439 Stats::Formula avgWrBW;
440 Stats::Formula avgConsumedRdBW;
441 Stats::Formula avgConsumedWrBW;
442 Stats::Formula peakBW;
443 Stats::Formula busUtil;
445 // Average queue lengths
446 Stats::Average avgRdQLen;
447 Stats::Average avgWrQLen;
449 // Row hit count and rate
450 Stats::Scalar readRowHits;
451 Stats::Scalar writeRowHits;
452 Stats::Formula readRowHitRate;
453 Stats::Formula writeRowHitRate;
454 Stats::Formula avgGap;
460 SimpleDRAM(const SimpleDRAMParams* p);
462 unsigned int drain(Event* de);
464 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
465 PortID idx = InvalidPortID);
468 virtual void startup();
472 Tick recvAtomic(PacketPtr pkt);
473 void recvFunctional(PacketPtr pkt);
474 bool recvTimingReq(PacketPtr pkt);
478 #endif //__MEM_SIMPLE_DRAM_HH__