src/mem/simple_mem.cc

   1 /*
   2  * Copyright (c) 2010-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  */
  44
  45 #include "base/random.hh"
  46 #include "mem/simple_mem.hh"
  47
  48 using namespace std;
  49
  50 SimpleMemory::SimpleMemory(const Params* p) :
  51     AbstractMemory(p),
  52     lat(p->latency), lat_var(p->latency_var)
  53 {
  54     for (size_t i = 0; i < p->port_port_connection_count; ++i) {
  55         ports.push_back(new MemoryPort(csprintf("%s-port-%d", name(), i),
  56                                        *this));
  57     }
  58 }
  59
  60 void
  61 SimpleMemory::init()
  62 {
  63     for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
  64          ++p) {
  65         if (!(*p)->isConnected()) {
  66             fatal("SimpleMemory port %s is unconnected!\n", (*p)->name());
  67         } else {
  68             (*p)->sendRangeChange();
  69         }
  70     }
  71 }
  72
  73 Tick
  74 SimpleMemory::calculateLatency(PacketPtr pkt)
  75 {
  76     if (pkt->memInhibitAsserted()) {
  77         return 0;
  78     } else {
  79         Tick latency = lat;
  80         if (lat_var != 0)
  81             latency += random_mt.random<Tick>(0, lat_var);
  82         return latency;
  83     }
  84 }
  85
  86 Tick
  87 SimpleMemory::doAtomicAccess(PacketPtr pkt)
  88 {
  89     access(pkt);
  90     return calculateLatency(pkt);
  91 }
  92
  93 void
  94 SimpleMemory::doFunctionalAccess(PacketPtr pkt)
  95 {
  96     functionalAccess(pkt);
  97 }
  98
  99 SlavePort &
 100 SimpleMemory::getSlavePort(const std::string &if_name, int idx)
 101 {
 102     if (if_name != "port") {
 103         return MemObject::getSlavePort(if_name, idx);
 104     } else {
 105         if (idx >= static_cast<int>(ports.size())) {
 106             fatal("SimpleMemory::getSlavePort: unknown index %d\n", idx);
 107         }
 108
 109         return *ports[idx];
 110     }
 111 }
 112
 113 unsigned int
 114 SimpleMemory::drain(Event *de)
 115 {
 116     int count = 0;
 117     for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
 118          ++p) {
 119         count += (*p)->drain(de);
 120     }
 121
 122     if (count)
 123         changeState(Draining);
 124     else
 125         changeState(Drained);
 126     return count;
 127 }
 128
 129 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
 130                                      SimpleMemory& _memory)
 131     : SimpleTimingPort(_name, &_memory), memory(_memory)
 132 { }
 133
 134 AddrRangeList
 135 SimpleMemory::MemoryPort::getAddrRanges()
 136 {
 137     AddrRangeList ranges;
 138     ranges.push_back(memory.getAddrRange());
 139     return ranges;
 140 }
 141
 142 Tick
 143 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 144 {
 145     return memory.doAtomicAccess(pkt);
 146 }
 147
 148 void
 149 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 150 {
 151     pkt->pushLabel(memory.name());
 152
 153     if (!queue.checkFunctional(pkt)) {
 154         // Default implementation of SimpleTimingPort::recvFunctional()
 155         // calls recvAtomic() and throws away the latency; we can save a
 156         // little here by just not calculating the latency.
 157         memory.doFunctionalAccess(pkt);
 158     }
 159
 160     pkt->popLabel();
 161 }
 162
 163 SimpleMemory*
 164 SimpleMemoryParams::create()
 165 {
 166     return new SimpleMemory(this);
 167 }