src/mem/simple_mem.cc

   1 /*
   2  * Copyright (c) 2010-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  */
  44
  45 #include "base/random.hh"
  46 #include "mem/simple_mem.hh"
  47
  48 using namespace std;
  49
  50 SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
  51     AbstractMemory(p),
  52     port(name() + ".port", *this), latency(p->latency),
  53     latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
  54     retryReq(false), retryResp(false),
  55     releaseEvent(this), dequeueEvent(this), drainManager(NULL)
  56 {
  57 }
  58
  59 void
  60 SimpleMemory::init()
  61 {
  62     // allow unconnected memories as this is used in several ruby
  63     // systems at the moment
  64     if (port.isConnected()) {
  65         port.sendRangeChange();
  66     }
  67 }
  68
  69 Tick
  70 SimpleMemory::recvAtomic(PacketPtr pkt)
  71 {
  72     access(pkt);
  73     return pkt->memInhibitAsserted() ? 0 : getLatency();
  74 }
  75
  76 void
  77 SimpleMemory::recvFunctional(PacketPtr pkt)
  78 {
  79     pkt->pushLabel(name());
  80
  81     functionalAccess(pkt);
  82
  83     // potentially update the packets in our packet queue as well
  84     for (auto i = packetQueue.begin(); i != packetQueue.end(); ++i)
  85         pkt->checkFunctional(i->pkt);
  86
  87     pkt->popLabel();
  88 }
  89
  90 bool
  91 SimpleMemory::recvTimingReq(PacketPtr pkt)
  92 {
  93     /// @todo temporary hack to deal with memory corruption issues until
  94     /// 4-phase transactions are complete
  95     for (int x = 0; x < pendingDelete.size(); x++)
  96         delete pendingDelete[x];
  97     pendingDelete.clear();
  98
  99     if (pkt->memInhibitAsserted()) {
 100         // snooper will supply based on copy of packet
 101         // still target's responsibility to delete packet
 102         pendingDelete.push_back(pkt);
 103         return true;
 104     }
 105
 106     // we should never get a new request after committing to retry the
 107     // current one, the bus violates the rule as it simply sends a
 108     // retry to the next one waiting on the retry list, so simply
 109     // ignore it
 110     if (retryReq)
 111         return false;
 112
 113     // if we are busy with a read or write, remember that we have to
 114     // retry
 115     if (isBusy) {
 116         retryReq = true;
 117         return false;
 118     }
 119
 120     // @todo someone should pay for this
 121     pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
 122
 123     // update the release time according to the bandwidth limit, and
 124     // do so with respect to the time it takes to finish this request
 125     // rather than long term as it is the short term data rate that is
 126     // limited for any real memory
 127
 128     // only look at reads and writes when determining if we are busy,
 129     // and for how long, as it is not clear what to regulate for the
 130     // other types of commands
 131     if (pkt->isRead() || pkt->isWrite()) {
 132         // calculate an appropriate tick to release to not exceed
 133         // the bandwidth limit
 134         Tick duration = pkt->getSize() * bandwidth;
 135
 136         // only consider ourselves busy if there is any need to wait
 137         // to avoid extra events being scheduled for (infinitely) fast
 138         // memories
 139         if (duration != 0) {
 140             schedule(releaseEvent, curTick() + duration);
 141             isBusy = true;
 142         }
 143     }
 144
 145     // go ahead and deal with the packet and put the response in the
 146     // queue if there is one
 147     bool needsResponse = pkt->needsResponse();
 148     recvAtomic(pkt);
 149     // turn packet around to go back to requester if response expected
 150     if (needsResponse) {
 151         // recvAtomic() should already have turned packet into
 152         // atomic response
 153         assert(pkt->isResponse());
 154         // to keep things simple (and in order), we put the packet at
 155         // the end even if the latency suggests it should be sent
 156         // before the packet(s) before it
 157         packetQueue.push_back(DeferredPacket(pkt, curTick() + getLatency()));
 158         if (!retryResp && !dequeueEvent.scheduled())
 159             schedule(dequeueEvent, packetQueue.back().tick);
 160     } else {
 161         pendingDelete.push_back(pkt);
 162     }
 163
 164     return true;
 165 }
 166
 167 void
 168 SimpleMemory::release()
 169 {
 170     assert(isBusy);
 171     isBusy = false;
 172     if (retryReq) {
 173         retryReq = false;
 174         port.sendRetry();
 175     }
 176 }
 177
 178 void
 179 SimpleMemory::dequeue()
 180 {
 181     assert(!packetQueue.empty());
 182     DeferredPacket deferred_pkt = packetQueue.front();
 183
 184     retryResp = !port.sendTimingResp(deferred_pkt.pkt);
 185
 186     if (!retryResp) {
 187         packetQueue.pop_front();
 188
 189         // if the queue is not empty, schedule the next dequeue event,
 190         // otherwise signal that we are drained if we were asked to do so
 191         if (!packetQueue.empty()) {
 192             // if there were packets that got in-between then we
 193             // already have an event scheduled, so use re-schedule
 194             reschedule(dequeueEvent,
 195                        std::max(packetQueue.front().tick, curTick()), true);
 196         } else if (drainManager) {
 197             drainManager->signalDrainDone();
 198             drainManager = NULL;
 199         }
 200     }
 201 }
 202
 203 Tick
 204 SimpleMemory::getLatency() const
 205 {
 206     return latency +
 207         (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
 208 }
 209
 210 void
 211 SimpleMemory::recvRetry()
 212 {
 213     assert(retryResp);
 214
 215     dequeue();
 216 }
 217
 218 BaseSlavePort &
 219 SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
 220 {
 221     if (if_name != "port") {
 222         return MemObject::getSlavePort(if_name, idx);
 223     } else {
 224         return port;
 225     }
 226 }
 227
 228 unsigned int
 229 SimpleMemory::drain(DrainManager *dm)
 230 {
 231     int count = 0;
 232
 233     // also track our internal queue
 234     if (!packetQueue.empty()) {
 235         count += 1;
 236         drainManager = dm;
 237     }
 238
 239     if (count)
 240         setDrainState(Drainable::Draining);
 241     else
 242         setDrainState(Drainable::Drained);
 243     return count;
 244 }
 245
 246 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
 247                                      SimpleMemory& _memory)
 248     : SlavePort(_name, &_memory), memory(_memory)
 249 { }
 250
 251 AddrRangeList
 252 SimpleMemory::MemoryPort::getAddrRanges() const
 253 {
 254     AddrRangeList ranges;
 255     ranges.push_back(memory.getAddrRange());
 256     return ranges;
 257 }
 258
 259 Tick
 260 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 261 {
 262     return memory.recvAtomic(pkt);
 263 }
 264
 265 void
 266 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 267 {
 268     memory.recvFunctional(pkt);
 269 }
 270
 271 bool
 272 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 273 {
 274     return memory.recvTimingReq(pkt);
 275 }
 276
 277 void
 278 SimpleMemory::MemoryPort::recvRetry()
 279 {
 280     memory.recvRetry();
 281 }
 282
 283 SimpleMemory*
 284 SimpleMemoryParams::create()
 285 {
 286     return new SimpleMemory(this);
 287 }