src/mem/simple_mem.cc

   1 /*
   2  * Copyright (c) 2010-2013, 2015 ARM Limited
   3  * All rights reserved
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   5  * The license below extends only to copyright in the software and shall
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   8  * to a hardware implementation of the functionality of the software
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  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
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  20  * notice, this list of conditions and the following disclaimer;
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  26  * this software without specific prior written permission.
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  40
  41 #include "mem/simple_mem.hh"
  42
  43 #include "base/random.hh"
  44 #include "base/trace.hh"
  45 #include "debug/Drain.hh"
  46
  47 SimpleMemory::SimpleMemory(const SimpleMemoryParams &p) :
  48     AbstractMemory(p),
  49     port(name() + ".port", *this), latency(p.latency),
  50     latency_var(p.latency_var), bandwidth(p.bandwidth), isBusy(false),
  51     retryReq(false), retryResp(false),
  52     releaseEvent([this]{ release(); }, name()),
  53     dequeueEvent([this]{ dequeue(); }, name())
  54 {
  55 }
  56
  57 void
  58 SimpleMemory::init()
  59 {
  60     AbstractMemory::init();
  61
  62     // allow unconnected memories as this is used in several ruby
  63     // systems at the moment
  64     if (port.isConnected()) {
  65         port.sendRangeChange();
  66     }
  67 }
  68
  69 Tick
  70 SimpleMemory::recvAtomic(PacketPtr pkt)
  71 {
  72     panic_if(pkt->cacheResponding(), "Should not see packets where cache "
  73              "is responding");
  74
  75     access(pkt);
  76     return getLatency();
  77 }
  78
  79 Tick
  80 SimpleMemory::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
  81 {
  82     Tick latency = recvAtomic(pkt);
  83
  84     if (backdoor.ptr())
  85         _backdoor = &backdoor;
  86     return latency;
  87 }
  88
  89 void
  90 SimpleMemory::recvFunctional(PacketPtr pkt)
  91 {
  92     pkt->pushLabel(name());
  93
  94     functionalAccess(pkt);
  95
  96     bool done = false;
  97     auto p = packetQueue.begin();
  98     // potentially update the packets in our packet queue as well
  99     while (!done && p != packetQueue.end()) {
 100         done = pkt->trySatisfyFunctional(p->pkt);
 101         ++p;
 102     }
 103
 104     pkt->popLabel();
 105 }
 106
 107 bool
 108 SimpleMemory::recvTimingReq(PacketPtr pkt)
 109 {
 110     panic_if(pkt->cacheResponding(), "Should not see packets where cache "
 111              "is responding");
 112
 113     panic_if(!(pkt->isRead() || pkt->isWrite()),
 114              "Should only see read and writes at memory controller, "
 115              "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
 116
 117     // we should not get a new request after committing to retry the
 118     // current one, but unfortunately the CPU violates this rule, so
 119     // simply ignore it for now
 120     if (retryReq)
 121         return false;
 122
 123     // if we are busy with a read or write, remember that we have to
 124     // retry
 125     if (isBusy) {
 126         retryReq = true;
 127         return false;
 128     }
 129
 130     // technically the packet only reaches us after the header delay,
 131     // and since this is a memory controller we also need to
 132     // deserialise the payload before performing any write operation
 133     Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
 134     pkt->headerDelay = pkt->payloadDelay = 0;
 135
 136     // update the release time according to the bandwidth limit, and
 137     // do so with respect to the time it takes to finish this request
 138     // rather than long term as it is the short term data rate that is
 139     // limited for any real memory
 140
 141     // calculate an appropriate tick to release to not exceed
 142     // the bandwidth limit
 143     Tick duration = pkt->getSize() * bandwidth;
 144
 145     // only consider ourselves busy if there is any need to wait
 146     // to avoid extra events being scheduled for (infinitely) fast
 147     // memories
 148     if (duration != 0) {
 149         schedule(releaseEvent, curTick() + duration);
 150         isBusy = true;
 151     }
 152
 153     // go ahead and deal with the packet and put the response in the
 154     // queue if there is one
 155     bool needsResponse = pkt->needsResponse();
 156     recvAtomic(pkt);
 157     // turn packet around to go back to requestor if response expected
 158     if (needsResponse) {
 159         // recvAtomic() should already have turned packet into
 160         // atomic response
 161         assert(pkt->isResponse());
 162
 163         Tick when_to_send = curTick() + receive_delay + getLatency();
 164
 165         // typically this should be added at the end, so start the
 166         // insertion sort with the last element, also make sure not to
 167         // re-order in front of some existing packet with the same
 168         // address, the latter is important as this memory effectively
 169         // hands out exclusive copies (shared is not asserted)
 170         auto i = packetQueue.end();
 171         --i;
 172         while (i != packetQueue.begin() && when_to_send < i->tick &&
 173                !i->pkt->matchAddr(pkt))
 174             --i;
 175
 176         // emplace inserts the element before the position pointed to by
 177         // the iterator, so advance it one step
 178         packetQueue.emplace(++i, pkt, when_to_send);
 179
 180         if (!retryResp && !dequeueEvent.scheduled())
 181             schedule(dequeueEvent, packetQueue.back().tick);
 182     } else {
 183         pendingDelete.reset(pkt);
 184     }
 185
 186     return true;
 187 }
 188
 189 void
 190 SimpleMemory::release()
 191 {
 192     assert(isBusy);
 193     isBusy = false;
 194     if (retryReq) {
 195         retryReq = false;
 196         port.sendRetryReq();
 197     }
 198 }
 199
 200 void
 201 SimpleMemory::dequeue()
 202 {
 203     assert(!packetQueue.empty());
 204     DeferredPacket deferred_pkt = packetQueue.front();
 205
 206     retryResp = !port.sendTimingResp(deferred_pkt.pkt);
 207
 208     if (!retryResp) {
 209         packetQueue.pop_front();
 210
 211         // if the queue is not empty, schedule the next dequeue event,
 212         // otherwise signal that we are drained if we were asked to do so
 213         if (!packetQueue.empty()) {
 214             // if there were packets that got in-between then we
 215             // already have an event scheduled, so use re-schedule
 216             reschedule(dequeueEvent,
 217                        std::max(packetQueue.front().tick, curTick()), true);
 218         } else if (drainState() == DrainState::Draining) {
 219             DPRINTF(Drain, "Draining of SimpleMemory complete\n");
 220             signalDrainDone();
 221         }
 222     }
 223 }
 224
 225 Tick
 226 SimpleMemory::getLatency() const
 227 {
 228     return latency +
 229         (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
 230 }
 231
 232 void
 233 SimpleMemory::recvRespRetry()
 234 {
 235     assert(retryResp);
 236
 237     dequeue();
 238 }
 239
 240 Port &
 241 SimpleMemory::getPort(const std::string &if_name, PortID idx)
 242 {
 243     if (if_name != "port") {
 244         return AbstractMemory::getPort(if_name, idx);
 245     } else {
 246         return port;
 247     }
 248 }
 249
 250 DrainState
 251 SimpleMemory::drain()
 252 {
 253     if (!packetQueue.empty()) {
 254         DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
 255         return DrainState::Draining;
 256     } else {
 257         return DrainState::Drained;
 258     }
 259 }
 260
 261 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
 262                                      SimpleMemory& _memory)
 263     : ResponsePort(_name, &_memory), memory(_memory)
 264 { }
 265
 266 AddrRangeList
 267 SimpleMemory::MemoryPort::getAddrRanges() const
 268 {
 269     AddrRangeList ranges;
 270     ranges.push_back(memory.getAddrRange());
 271     return ranges;
 272 }
 273
 274 Tick
 275 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 276 {
 277     return memory.recvAtomic(pkt);
 278 }
 279
 280 Tick
 281 SimpleMemory::MemoryPort::recvAtomicBackdoor(
 282         PacketPtr pkt, MemBackdoorPtr &_backdoor)
 283 {
 284     return memory.recvAtomicBackdoor(pkt, _backdoor);
 285 }
 286
 287 void
 288 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 289 {
 290     memory.recvFunctional(pkt);
 291 }
 292
 293 bool
 294 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 295 {
 296     return memory.recvTimingReq(pkt);
 297 }
 298
 299 void
 300 SimpleMemory::MemoryPort::recvRespRetry()
 301 {
 302     memory.recvRespRetry();
 303 }