src/mem/simple_mem.cc

   1 /*
   2  * Copyright (c) 2010-2013, 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  */
  44
  45 #include "mem/simple_mem.hh"
  46
  47 #include "base/random.hh"
  48 #include "base/trace.hh"
  49 #include "debug/Drain.hh"
  50
  51 using namespace std;
  52
  53 SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
  54     AbstractMemory(p),
  55     port(name() + ".port", *this), latency(p->latency),
  56     latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
  57     retryReq(false), retryResp(false),
  58     releaseEvent([this]{ release(); }, name()),
  59     dequeueEvent([this]{ dequeue(); }, name())
  60 {
  61 }
  62
  63 void
  64 SimpleMemory::init()
  65 {
  66     AbstractMemory::init();
  67
  68     // allow unconnected memories as this is used in several ruby
  69     // systems at the moment
  70     if (port.isConnected()) {
  71         port.sendRangeChange();
  72     }
  73 }
  74
  75 Tick
  76 SimpleMemory::recvAtomic(PacketPtr pkt)
  77 {
  78     panic_if(pkt->cacheResponding(), "Should not see packets where cache "
  79              "is responding");
  80
  81     access(pkt);
  82     return getLatency();
  83 }
  84
  85 void
  86 SimpleMemory::recvFunctional(PacketPtr pkt)
  87 {
  88     pkt->pushLabel(name());
  89
  90     functionalAccess(pkt);
  91
  92     bool done = false;
  93     auto p = packetQueue.begin();
  94     // potentially update the packets in our packet queue as well
  95     while (!done && p != packetQueue.end()) {
  96         done = pkt->checkFunctional(p->pkt);
  97         ++p;
  98     }
  99
 100     pkt->popLabel();
 101 }
 102
 103 bool
 104 SimpleMemory::recvTimingReq(PacketPtr pkt)
 105 {
 106     panic_if(pkt->cacheResponding(), "Should not see packets where cache "
 107              "is responding");
 108
 109     panic_if(!(pkt->isRead() || pkt->isWrite()),
 110              "Should only see read and writes at memory controller, "
 111              "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
 112
 113     // we should not get a new request after committing to retry the
 114     // current one, but unfortunately the CPU violates this rule, so
 115     // simply ignore it for now
 116     if (retryReq)
 117         return false;
 118
 119     // if we are busy with a read or write, remember that we have to
 120     // retry
 121     if (isBusy) {
 122         retryReq = true;
 123         return false;
 124     }
 125
 126     // technically the packet only reaches us after the header delay,
 127     // and since this is a memory controller we also need to
 128     // deserialise the payload before performing any write operation
 129     Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
 130     pkt->headerDelay = pkt->payloadDelay = 0;
 131
 132     // update the release time according to the bandwidth limit, and
 133     // do so with respect to the time it takes to finish this request
 134     // rather than long term as it is the short term data rate that is
 135     // limited for any real memory
 136
 137     // calculate an appropriate tick to release to not exceed
 138     // the bandwidth limit
 139     Tick duration = pkt->getSize() * bandwidth;
 140
 141     // only consider ourselves busy if there is any need to wait
 142     // to avoid extra events being scheduled for (infinitely) fast
 143     // memories
 144     if (duration != 0) {
 145         schedule(releaseEvent, curTick() + duration);
 146         isBusy = true;
 147     }
 148
 149     // go ahead and deal with the packet and put the response in the
 150     // queue if there is one
 151     bool needsResponse = pkt->needsResponse();
 152     recvAtomic(pkt);
 153     // turn packet around to go back to requester if response expected
 154     if (needsResponse) {
 155         // recvAtomic() should already have turned packet into
 156         // atomic response
 157         assert(pkt->isResponse());
 158
 159         Tick when_to_send = curTick() + receive_delay + getLatency();
 160
 161         // typically this should be added at the end, so start the
 162         // insertion sort with the last element, also make sure not to
 163         // re-order in front of some existing packet with the same
 164         // address, the latter is important as this memory effectively
 165         // hands out exclusive copies (shared is not asserted)
 166         auto i = packetQueue.end();
 167         --i;
 168         while (i != packetQueue.begin() && when_to_send < i->tick &&
 169                i->pkt->getAddr() != pkt->getAddr())
 170             --i;
 171
 172         // emplace inserts the element before the position pointed to by
 173         // the iterator, so advance it one step
 174         packetQueue.emplace(++i, pkt, when_to_send);
 175
 176         if (!retryResp && !dequeueEvent.scheduled())
 177             schedule(dequeueEvent, packetQueue.back().tick);
 178     } else {
 179         pendingDelete.reset(pkt);
 180     }
 181
 182     return true;
 183 }
 184
 185 void
 186 SimpleMemory::release()
 187 {
 188     assert(isBusy);
 189     isBusy = false;
 190     if (retryReq) {
 191         retryReq = false;
 192         port.sendRetryReq();
 193     }
 194 }
 195
 196 void
 197 SimpleMemory::dequeue()
 198 {
 199     assert(!packetQueue.empty());
 200     DeferredPacket deferred_pkt = packetQueue.front();
 201
 202     retryResp = !port.sendTimingResp(deferred_pkt.pkt);
 203
 204     if (!retryResp) {
 205         packetQueue.pop_front();
 206
 207         // if the queue is not empty, schedule the next dequeue event,
 208         // otherwise signal that we are drained if we were asked to do so
 209         if (!packetQueue.empty()) {
 210             // if there were packets that got in-between then we
 211             // already have an event scheduled, so use re-schedule
 212             reschedule(dequeueEvent,
 213                        std::max(packetQueue.front().tick, curTick()), true);
 214         } else if (drainState() == DrainState::Draining) {
 215             DPRINTF(Drain, "Draining of SimpleMemory complete\n");
 216             signalDrainDone();
 217         }
 218     }
 219 }
 220
 221 Tick
 222 SimpleMemory::getLatency() const
 223 {
 224     return latency +
 225         (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
 226 }
 227
 228 void
 229 SimpleMemory::recvRespRetry()
 230 {
 231     assert(retryResp);
 232
 233     dequeue();
 234 }
 235
 236 BaseSlavePort &
 237 SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
 238 {
 239     if (if_name != "port") {
 240         return MemObject::getSlavePort(if_name, idx);
 241     } else {
 242         return port;
 243     }
 244 }
 245
 246 DrainState
 247 SimpleMemory::drain()
 248 {
 249     if (!packetQueue.empty()) {
 250         DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
 251         return DrainState::Draining;
 252     } else {
 253         return DrainState::Drained;
 254     }
 255 }
 256
 257 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
 258                                      SimpleMemory& _memory)
 259     : SlavePort(_name, &_memory), memory(_memory)
 260 { }
 261
 262 AddrRangeList
 263 SimpleMemory::MemoryPort::getAddrRanges() const
 264 {
 265     AddrRangeList ranges;
 266     ranges.push_back(memory.getAddrRange());
 267     return ranges;
 268 }
 269
 270 Tick
 271 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 272 {
 273     return memory.recvAtomic(pkt);
 274 }
 275
 276 void
 277 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 278 {
 279     memory.recvFunctional(pkt);
 280 }
 281
 282 bool
 283 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 284 {
 285     return memory.recvTimingReq(pkt);
 286 }
 287
 288 void
 289 SimpleMemory::MemoryPort::recvRespRetry()
 290 {
 291     memory.recvRespRetry();
 292 }
 293
 294 SimpleMemory*
 295 SimpleMemoryParams::create()
 296 {
 297     return new SimpleMemory(this);
 298 }