src/mem/simple_mem.cc

   1 /*
   2  * Copyright (c) 2010-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  */
  44
  45 #include "base/random.hh"
  46 #include "mem/simple_mem.hh"
  47
  48 using namespace std;
  49
  50 SimpleMemory::SimpleMemory(const Params* p) :
  51     AbstractMemory(p),
  52     port(name() + ".port", *this), lat(p->latency), lat_var(p->latency_var)
  53 {
  54 }
  55
  56 void
  57 SimpleMemory::init()
  58 {
  59     // allow unconnected memories as this is used in several ruby
  60     // systems at the moment
  61     if (port.isConnected()) {
  62         port.sendRangeChange();
  63     }
  64 }
  65
  66 Tick
  67 SimpleMemory::calculateLatency(PacketPtr pkt)
  68 {
  69     if (pkt->memInhibitAsserted()) {
  70         return 0;
  71     } else {
  72         Tick latency = lat;
  73         if (lat_var != 0)
  74             latency += random_mt.random<Tick>(0, lat_var);
  75         return latency;
  76     }
  77 }
  78
  79 Tick
  80 SimpleMemory::doAtomicAccess(PacketPtr pkt)
  81 {
  82     access(pkt);
  83     return calculateLatency(pkt);
  84 }
  85
  86 void
  87 SimpleMemory::doFunctionalAccess(PacketPtr pkt)
  88 {
  89     functionalAccess(pkt);
  90 }
  91
  92 SlavePort &
  93 SimpleMemory::getSlavePort(const std::string &if_name, int idx)
  94 {
  95     if (if_name != "port") {
  96         return MemObject::getSlavePort(if_name, idx);
  97     } else {
  98         return port;
  99     }
 100 }
 101
 102 unsigned int
 103 SimpleMemory::drain(Event *de)
 104 {
 105     int count = port.drain(de);
 106
 107     if (count)
 108         changeState(Draining);
 109     else
 110         changeState(Drained);
 111     return count;
 112 }
 113
 114 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
 115                                      SimpleMemory& _memory)
 116     : SimpleTimingPort(_name, &_memory), memory(_memory)
 117 { }
 118
 119 AddrRangeList
 120 SimpleMemory::MemoryPort::getAddrRanges() const
 121 {
 122     AddrRangeList ranges;
 123     ranges.push_back(memory.getAddrRange());
 124     return ranges;
 125 }
 126
 127 Tick
 128 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 129 {
 130     return memory.doAtomicAccess(pkt);
 131 }
 132
 133 void
 134 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 135 {
 136     pkt->pushLabel(memory.name());
 137
 138     if (!queue.checkFunctional(pkt)) {
 139         // Default implementation of SimpleTimingPort::recvFunctional()
 140         // calls recvAtomic() and throws away the latency; we can save a
 141         // little here by just not calculating the latency.
 142         memory.doFunctionalAccess(pkt);
 143     }
 144
 145     pkt->popLabel();
 146 }
 147
 148 SimpleMemory*
 149 SimpleMemoryParams::create()
 150 {
 151     return new SimpleMemory(this);
 152 }