2 * Copyright (c) 2010-2012 ARM Limited
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
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23 * documentation and/or other materials provided with the distribution;
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Ron Dreslinski
45 #include "base/random.hh"
46 #include "mem/simple_mem.hh"
50 SimpleMemory::SimpleMemory(const SimpleMemoryParams
* p
) :
52 port(name() + ".port", *this), lat(p
->latency
),
53 lat_var(p
->latency_var
), bandwidth(p
->bandwidth
),
54 isBusy(false), retryReq(false), releaseEvent(this)
61 // allow unconnected memories as this is used in several ruby
62 // systems at the moment
63 if (port
.isConnected()) {
64 port
.sendRangeChange();
69 SimpleMemory::calculateLatency(PacketPtr pkt
)
71 if (pkt
->memInhibitAsserted()) {
76 latency
+= random_mt
.random
<Tick
>(0, lat_var
);
82 SimpleMemory::doAtomicAccess(PacketPtr pkt
)
85 return calculateLatency(pkt
);
89 SimpleMemory::doFunctionalAccess(PacketPtr pkt
)
91 functionalAccess(pkt
);
95 SimpleMemory::recvTimingReq(PacketPtr pkt
)
97 /// @todo temporary hack to deal with memory corruption issues until
98 /// 4-phase transactions are complete
99 for (int x
= 0; x
< pendingDelete
.size(); x
++)
100 delete pendingDelete
[x
];
101 pendingDelete
.clear();
103 if (pkt
->memInhibitAsserted()) {
104 // snooper will supply based on copy of packet
105 // still target's responsibility to delete packet
106 pendingDelete
.push_back(pkt
);
110 // we should never get a new request after committing to retry the
111 // current one, the bus violates the rule as it simply sends a
112 // retry to the next one waiting on the retry list, so simply
117 // if we are busy with a read or write, remember that we have to
124 // update the release time according to the bandwidth limit, and
125 // do so with respect to the time it takes to finish this request
126 // rather than long term as it is the short term data rate that is
127 // limited for any real memory
129 // only look at reads and writes when determining if we are busy,
130 // and for how long, as it is not clear what to regulate for the
131 // other types of commands
132 if (pkt
->isRead() || pkt
->isWrite()) {
133 // calculate an appropriate tick to release to not exceed
134 // the bandwidth limit
135 Tick duration
= pkt
->getSize() * bandwidth
;
137 // only consider ourselves busy if there is any need to wait
138 // to avoid extra events being scheduled for (infinitely) fast
141 schedule(releaseEvent
, curTick() + duration
);
146 // go ahead and deal with the packet and put the response in the
147 // queue if there is one
148 bool needsResponse
= pkt
->needsResponse();
149 Tick latency
= doAtomicAccess(pkt
);
150 // turn packet around to go back to requester if response expected
152 // doAtomicAccess() should already have turned packet into
154 assert(pkt
->isResponse());
155 port
.schedTimingResp(pkt
, curTick() + latency
);
164 SimpleMemory::release()
175 SimpleMemory::getSlavePort(const std::string
&if_name
, PortID idx
)
177 if (if_name
!= "port") {
178 return MemObject::getSlavePort(if_name
, idx
);
185 SimpleMemory::drain(DrainManager
*dm
)
187 int count
= port
.drain(dm
);
190 setDrainState(Drainable::Draining
);
192 setDrainState(Drainable::Drained
);
196 SimpleMemory::MemoryPort::MemoryPort(const std::string
& _name
,
197 SimpleMemory
& _memory
)
198 : QueuedSlavePort(_name
, &_memory
, queueImpl
),
199 queueImpl(_memory
, *this), memory(_memory
)
203 SimpleMemory::MemoryPort::getAddrRanges() const
205 AddrRangeList ranges
;
206 ranges
.push_back(memory
.getAddrRange());
211 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt
)
213 return memory
.doAtomicAccess(pkt
);
217 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt
)
219 pkt
->pushLabel(memory
.name());
221 if (!queue
.checkFunctional(pkt
)) {
222 // Default implementation of SimpleTimingPort::recvFunctional()
223 // calls recvAtomic() and throws away the latency; we can save a
224 // little here by just not calculating the latency.
225 memory
.doFunctionalAccess(pkt
);
232 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt
)
234 return memory
.recvTimingReq(pkt
);
238 SimpleMemoryParams::create()
240 return new SimpleMemory(this);