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40 * Authors: Ron Dreslinski
45 #include "mem/simple_mem.hh"
47 #include "base/random.hh"
48 #include "base/trace.hh"
49 #include "debug/Drain.hh"
51 SimpleMemory::SimpleMemory(const SimpleMemoryParams
* p
) :
53 port(name() + ".port", *this), latency(p
->latency
),
54 latency_var(p
->latency_var
), bandwidth(p
->bandwidth
), isBusy(false),
55 retryReq(false), retryResp(false),
56 releaseEvent([this]{ release(); }, name()),
57 dequeueEvent([this]{ dequeue(); }, name())
64 AbstractMemory::init();
66 // allow unconnected memories as this is used in several ruby
67 // systems at the moment
68 if (port
.isConnected()) {
69 port
.sendRangeChange();
74 SimpleMemory::recvAtomic(PacketPtr pkt
)
76 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
84 SimpleMemory::recvAtomicBackdoor(PacketPtr pkt
, MemBackdoorPtr
&_backdoor
)
86 Tick latency
= recvAtomic(pkt
);
89 _backdoor
= &backdoor
;
94 SimpleMemory::recvFunctional(PacketPtr pkt
)
96 pkt
->pushLabel(name());
98 functionalAccess(pkt
);
101 auto p
= packetQueue
.begin();
102 // potentially update the packets in our packet queue as well
103 while (!done
&& p
!= packetQueue
.end()) {
104 done
= pkt
->trySatisfyFunctional(p
->pkt
);
112 SimpleMemory::recvTimingReq(PacketPtr pkt
)
114 panic_if(pkt
->cacheResponding(), "Should not see packets where cache "
117 panic_if(!(pkt
->isRead() || pkt
->isWrite()),
118 "Should only see read and writes at memory controller, "
119 "saw %s to %#llx\n", pkt
->cmdString(), pkt
->getAddr());
121 // we should not get a new request after committing to retry the
122 // current one, but unfortunately the CPU violates this rule, so
123 // simply ignore it for now
127 // if we are busy with a read or write, remember that we have to
134 // technically the packet only reaches us after the header delay,
135 // and since this is a memory controller we also need to
136 // deserialise the payload before performing any write operation
137 Tick receive_delay
= pkt
->headerDelay
+ pkt
->payloadDelay
;
138 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
140 // update the release time according to the bandwidth limit, and
141 // do so with respect to the time it takes to finish this request
142 // rather than long term as it is the short term data rate that is
143 // limited for any real memory
145 // calculate an appropriate tick to release to not exceed
146 // the bandwidth limit
147 Tick duration
= pkt
->getSize() * bandwidth
;
149 // only consider ourselves busy if there is any need to wait
150 // to avoid extra events being scheduled for (infinitely) fast
153 schedule(releaseEvent
, curTick() + duration
);
157 // go ahead and deal with the packet and put the response in the
158 // queue if there is one
159 bool needsResponse
= pkt
->needsResponse();
161 // turn packet around to go back to requester if response expected
163 // recvAtomic() should already have turned packet into
165 assert(pkt
->isResponse());
167 Tick when_to_send
= curTick() + receive_delay
+ getLatency();
169 // typically this should be added at the end, so start the
170 // insertion sort with the last element, also make sure not to
171 // re-order in front of some existing packet with the same
172 // address, the latter is important as this memory effectively
173 // hands out exclusive copies (shared is not asserted)
174 auto i
= packetQueue
.end();
176 while (i
!= packetQueue
.begin() && when_to_send
< i
->tick
&&
177 !i
->pkt
->matchAddr(pkt
))
180 // emplace inserts the element before the position pointed to by
181 // the iterator, so advance it one step
182 packetQueue
.emplace(++i
, pkt
, when_to_send
);
184 if (!retryResp
&& !dequeueEvent
.scheduled())
185 schedule(dequeueEvent
, packetQueue
.back().tick
);
187 pendingDelete
.reset(pkt
);
194 SimpleMemory::release()
205 SimpleMemory::dequeue()
207 assert(!packetQueue
.empty());
208 DeferredPacket deferred_pkt
= packetQueue
.front();
210 retryResp
= !port
.sendTimingResp(deferred_pkt
.pkt
);
213 packetQueue
.pop_front();
215 // if the queue is not empty, schedule the next dequeue event,
216 // otherwise signal that we are drained if we were asked to do so
217 if (!packetQueue
.empty()) {
218 // if there were packets that got in-between then we
219 // already have an event scheduled, so use re-schedule
220 reschedule(dequeueEvent
,
221 std::max(packetQueue
.front().tick
, curTick()), true);
222 } else if (drainState() == DrainState::Draining
) {
223 DPRINTF(Drain
, "Draining of SimpleMemory complete\n");
230 SimpleMemory::getLatency() const
233 (latency_var
? random_mt
.random
<Tick
>(0, latency_var
) : 0);
237 SimpleMemory::recvRespRetry()
245 SimpleMemory::getPort(const std::string
&if_name
, PortID idx
)
247 if (if_name
!= "port") {
248 return MemObject::getPort(if_name
, idx
);
255 SimpleMemory::drain()
257 if (!packetQueue
.empty()) {
258 DPRINTF(Drain
, "SimpleMemory Queue has requests, waiting to drain\n");
259 return DrainState::Draining
;
261 return DrainState::Drained
;
265 SimpleMemory::MemoryPort::MemoryPort(const std::string
& _name
,
266 SimpleMemory
& _memory
)
267 : SlavePort(_name
, &_memory
), memory(_memory
)
271 SimpleMemory::MemoryPort::getAddrRanges() const
273 AddrRangeList ranges
;
274 ranges
.push_back(memory
.getAddrRange());
279 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt
)
281 return memory
.recvAtomic(pkt
);
285 SimpleMemory::MemoryPort::recvAtomicBackdoor(
286 PacketPtr pkt
, MemBackdoorPtr
&_backdoor
)
288 return memory
.recvAtomicBackdoor(pkt
, _backdoor
);
292 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt
)
294 memory
.recvFunctional(pkt
);
298 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt
)
300 return memory
.recvTimingReq(pkt
);
304 SimpleMemory::MemoryPort::recvRespRetry()
306 memory
.recvRespRetry();
310 SimpleMemoryParams::create()
312 return new SimpleMemory(this);