src/mem/simple_mem.cc

   1 /*
   2  * Copyright (c) 2010-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Ali Saidi
  42  *          Andreas Hansson
  43  */
  44
  45 #include "base/random.hh"
  46 #include "mem/simple_mem.hh"
  47 #include "debug/Drain.hh"
  48
  49 using namespace std;
  50
  51 SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
  52     AbstractMemory(p),
  53     port(name() + ".port", *this), latency(p->latency),
  54     latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
  55     retryReq(false), retryResp(false),
  56     releaseEvent(this), dequeueEvent(this)
  57 {
  58 }
  59
  60 void
  61 SimpleMemory::init()
  62 {
  63     AbstractMemory::init();
  64
  65     // allow unconnected memories as this is used in several ruby
  66     // systems at the moment
  67     if (port.isConnected()) {
  68         port.sendRangeChange();
  69     }
  70 }
  71
  72 Tick
  73 SimpleMemory::recvAtomic(PacketPtr pkt)
  74 {
  75     access(pkt);
  76     return pkt->memInhibitAsserted() ? 0 : getLatency();
  77 }
  78
  79 void
  80 SimpleMemory::recvFunctional(PacketPtr pkt)
  81 {
  82     pkt->pushLabel(name());
  83
  84     functionalAccess(pkt);
  85
  86     bool done = false;
  87     auto p = packetQueue.begin();
  88     // potentially update the packets in our packet queue as well
  89     while (!done && p != packetQueue.end()) {
  90         done = pkt->checkFunctional(p->pkt);
  91         ++p;
  92     }
  93
  94     pkt->popLabel();
  95 }
  96
  97 bool
  98 SimpleMemory::recvTimingReq(PacketPtr pkt)
  99 {
 100     if (pkt->memInhibitAsserted()) {
 101         // snooper will supply based on copy of packet
 102         // still target's responsibility to delete packet
 103         pendingDelete.reset(pkt);
 104         return true;
 105     }
 106
 107     // we should never get a new request after committing to retry the
 108     // current one, the bus violates the rule as it simply sends a
 109     // retry to the next one waiting on the retry list, so simply
 110     // ignore it
 111     if (retryReq)
 112         return false;
 113
 114     // if we are busy with a read or write, remember that we have to
 115     // retry
 116     if (isBusy) {
 117         retryReq = true;
 118         return false;
 119     }
 120
 121     // @todo someone should pay for this
 122     pkt->headerDelay = pkt->payloadDelay = 0;
 123
 124     // update the release time according to the bandwidth limit, and
 125     // do so with respect to the time it takes to finish this request
 126     // rather than long term as it is the short term data rate that is
 127     // limited for any real memory
 128
 129     // only look at reads and writes when determining if we are busy,
 130     // and for how long, as it is not clear what to regulate for the
 131     // other types of commands
 132     if (pkt->isRead() || pkt->isWrite()) {
 133         // calculate an appropriate tick to release to not exceed
 134         // the bandwidth limit
 135         Tick duration = pkt->getSize() * bandwidth;
 136
 137         // only consider ourselves busy if there is any need to wait
 138         // to avoid extra events being scheduled for (infinitely) fast
 139         // memories
 140         if (duration != 0) {
 141             schedule(releaseEvent, curTick() + duration);
 142             isBusy = true;
 143         }
 144     }
 145
 146     // go ahead and deal with the packet and put the response in the
 147     // queue if there is one
 148     bool needsResponse = pkt->needsResponse();
 149     recvAtomic(pkt);
 150     // turn packet around to go back to requester if response expected
 151     if (needsResponse) {
 152         // recvAtomic() should already have turned packet into
 153         // atomic response
 154         assert(pkt->isResponse());
 155         // to keep things simple (and in order), we put the packet at
 156         // the end even if the latency suggests it should be sent
 157         // before the packet(s) before it
 158         packetQueue.emplace_back(pkt, curTick() + getLatency());
 159         if (!retryResp && !dequeueEvent.scheduled())
 160             schedule(dequeueEvent, packetQueue.back().tick);
 161     } else {
 162         pendingDelete.reset(pkt);
 163     }
 164
 165     return true;
 166 }
 167
 168 void
 169 SimpleMemory::release()
 170 {
 171     assert(isBusy);
 172     isBusy = false;
 173     if (retryReq) {
 174         retryReq = false;
 175         port.sendRetryReq();
 176     }
 177 }
 178
 179 void
 180 SimpleMemory::dequeue()
 181 {
 182     assert(!packetQueue.empty());
 183     DeferredPacket deferred_pkt = packetQueue.front();
 184
 185     retryResp = !port.sendTimingResp(deferred_pkt.pkt);
 186
 187     if (!retryResp) {
 188         packetQueue.pop_front();
 189
 190         // if the queue is not empty, schedule the next dequeue event,
 191         // otherwise signal that we are drained if we were asked to do so
 192         if (!packetQueue.empty()) {
 193             // if there were packets that got in-between then we
 194             // already have an event scheduled, so use re-schedule
 195             reschedule(dequeueEvent,
 196                        std::max(packetQueue.front().tick, curTick()), true);
 197         } else if (drainState() == DrainState::Draining) {
 198             DPRINTF(Drain, "Draining of SimpleMemory complete\n");
 199             signalDrainDone();
 200         }
 201     }
 202 }
 203
 204 Tick
 205 SimpleMemory::getLatency() const
 206 {
 207     return latency +
 208         (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
 209 }
 210
 211 void
 212 SimpleMemory::recvRespRetry()
 213 {
 214     assert(retryResp);
 215
 216     dequeue();
 217 }
 218
 219 BaseSlavePort &
 220 SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
 221 {
 222     if (if_name != "port") {
 223         return MemObject::getSlavePort(if_name, idx);
 224     } else {
 225         return port;
 226     }
 227 }
 228
 229 DrainState
 230 SimpleMemory::drain()
 231 {
 232     if (!packetQueue.empty()) {
 233         DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
 234         return DrainState::Draining;
 235     } else {
 236         return DrainState::Drained;
 237     }
 238 }
 239
 240 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
 241                                      SimpleMemory& _memory)
 242     : SlavePort(_name, &_memory), memory(_memory)
 243 { }
 244
 245 AddrRangeList
 246 SimpleMemory::MemoryPort::getAddrRanges() const
 247 {
 248     AddrRangeList ranges;
 249     ranges.push_back(memory.getAddrRange());
 250     return ranges;
 251 }
 252
 253 Tick
 254 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 255 {
 256     return memory.recvAtomic(pkt);
 257 }
 258
 259 void
 260 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 261 {
 262     memory.recvFunctional(pkt);
 263 }
 264
 265 bool
 266 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 267 {
 268     return memory.recvTimingReq(pkt);
 269 }
 270
 271 void
 272 SimpleMemory::MemoryPort::recvRespRetry()
 273 {
 274     memory.recvRespRetry();
 275 }
 276
 277 SimpleMemory*
 278 SimpleMemoryParams::create()
 279 {
 280     return new SimpleMemory(this);
 281 }