src/mem/simple_mem.hh

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /**
  42  * @file
  43  * SimpleMemory declaration
  44  */
  45
  46 #ifndef __MEM_SIMPLE_MEMORY_HH__
  47 #define __MEM_SIMPLE_MEMORY_HH__
  48
  49 #include <list>
  50
  51 #include "mem/abstract_mem.hh"
  52 #include "mem/port.hh"
  53 #include "params/SimpleMemory.hh"
  54
  55 /**
  56  * The simple memory is a basic single-ported memory controller with
  57  * a configurable throughput and latency.
  58  *
  59  * @sa  \ref gem5MemorySystem "gem5 Memory System"
  60  */
  61 class SimpleMemory : public AbstractMemory
  62 {
  63
  64   private:
  65
  66     /**
  67      * A deferred packet stores a packet along with its scheduled
  68      * transmission time
  69      */
  70     class DeferredPacket
  71     {
  72
  73       public:
  74
  75         const Tick tick;
  76         const PacketPtr pkt;
  77
  78         DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
  79         { }
  80     };
  81
  82     class MemoryPort : public ResponsePort
  83     {
  84       private:
  85         SimpleMemory& memory;
  86
  87       public:
  88         MemoryPort(const std::string& _name, SimpleMemory& _memory);
  89
  90       protected:
  91         Tick recvAtomic(PacketPtr pkt) override;
  92         Tick recvAtomicBackdoor(
  93                 PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
  94         void recvFunctional(PacketPtr pkt) override;
  95         bool recvTimingReq(PacketPtr pkt) override;
  96         void recvRespRetry() override;
  97         AddrRangeList getAddrRanges() const override;
  98     };
  99
 100     MemoryPort port;
 101
 102     /**
 103      * Latency from that a request is accepted until the response is
 104      * ready to be sent.
 105      */
 106     const Tick latency;
 107
 108     /**
 109      * Fudge factor added to the latency.
 110      */
 111     const Tick latency_var;
 112
 113     /**
 114      * Internal (unbounded) storage to mimic the delay caused by the
 115      * actual memory access. Note that this is where the packet spends
 116      * the memory latency.
 117      */
 118     std::list<DeferredPacket> packetQueue;
 119
 120     /**
 121      * Bandwidth in ticks per byte. The regulation affects the
 122      * acceptance rate of requests and the queueing takes place after
 123      * the regulation.
 124      */
 125     const double bandwidth;
 126
 127     /**
 128      * Track the state of the memory as either idle or busy, no need
 129      * for an enum with only two states.
 130      */
 131     bool isBusy;
 132
 133     /**
 134      * Remember if we have to retry an outstanding request that
 135      * arrived while we were busy.
 136      */
 137     bool retryReq;
 138
 139     /**
 140      * Remember if we failed to send a response and are awaiting a
 141      * retry. This is only used as a check.
 142      */
 143     bool retryResp;
 144
 145     /**
 146      * Release the memory after being busy and send a retry if a
 147      * request was rejected in the meanwhile.
 148      */
 149     void release();
 150
 151     EventFunctionWrapper releaseEvent;
 152
 153     /**
 154      * Dequeue a packet from our internal packet queue and move it to
 155      * the port where it will be sent as soon as possible.
 156      */
 157     void dequeue();
 158
 159     EventFunctionWrapper dequeueEvent;
 160
 161     /**
 162      * Detemine the latency.
 163      *
 164      * @return the latency seen by the current packet
 165      */
 166     Tick getLatency() const;
 167
 168     /**
 169      * Upstream caches need this packet until true is returned, so
 170      * hold it for deletion until a subsequent call
 171      */
 172     std::unique_ptr<Packet> pendingDelete;
 173
 174   public:
 175
 176     SimpleMemory(const SimpleMemoryParams &p);
 177
 178     DrainState drain() override;
 179
 180     Port &getPort(const std::string &if_name,
 181                   PortID idx=InvalidPortID) override;
 182     void init() override;
 183
 184   protected:
 185     Tick recvAtomic(PacketPtr pkt);
 186     Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor);
 187     void recvFunctional(PacketPtr pkt);
 188     bool recvTimingReq(PacketPtr pkt);
 189     void recvRespRetry();
 190 };
 191
 192 #endif //__MEM_SIMPLE_MEMORY_HH__