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40 * Authors: Ron Dreslinski
46 * SimpleMemory declaration
49 #ifndef __SIMPLE_MEMORY_HH__
50 #define __SIMPLE_MEMORY_HH__
54 #include "mem/abstract_mem.hh"
55 #include "mem/port.hh"
56 #include "params/SimpleMemory.hh"
59 * The simple memory is a basic single-ported memory controller with
60 * a configurable throughput and latency.
62 * @sa \ref gem5MemorySystem "gem5 Memory System"
64 class SimpleMemory : public AbstractMemory
70 * A deferred packet stores a packet along with its scheduled
81 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
85 class MemoryPort : public SlavePort
94 MemoryPort(const std::string& _name, SimpleMemory& _memory);
98 Tick recvAtomic(PacketPtr pkt);
100 void recvFunctional(PacketPtr pkt);
102 bool recvTimingReq(PacketPtr pkt);
104 void recvRespRetry();
106 AddrRangeList getAddrRanges() const;
113 * Latency from that a request is accepted until the response is
119 * Fudge factor added to the latency.
121 const Tick latency_var;
124 * Internal (unbounded) storage to mimic the delay caused by the
125 * actual memory access. Note that this is where the packet spends
126 * the memory latency.
128 std::list<DeferredPacket> packetQueue;
131 * Bandwidth in ticks per byte. The regulation affects the
132 * acceptance rate of requests and the queueing takes place after
135 const double bandwidth;
138 * Track the state of the memory as either idle or busy, no need
139 * for an enum with only two states.
144 * Remember if we have to retry an outstanding request that
145 * arrived while we were busy.
150 * Remember if we failed to send a response and are awaiting a
151 * retry. This is only used as a check.
156 * Release the memory after being busy and send a retry if a
157 * request was rejected in the meanwhile.
161 EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
164 * Dequeue a packet from our internal packet queue and move it to
165 * the port where it will be sent as soon as possible.
169 EventWrapper<SimpleMemory, &SimpleMemory::dequeue> dequeueEvent;
172 * Detemine the latency.
174 * @return the latency seen by the current packet
176 Tick getLatency() const;
179 * Upstream caches need this packet until true is returned, so
180 * hold it for deletion until a subsequent call
182 std::unique_ptr<Packet> pendingDelete;
186 SimpleMemory(const SimpleMemoryParams *p);
188 DrainState drain() override;
190 BaseSlavePort& getSlavePort(const std::string& if_name,
191 PortID idx = InvalidPortID) override;
192 void init() override;
196 Tick recvAtomic(PacketPtr pkt);
198 void recvFunctional(PacketPtr pkt);
200 bool recvTimingReq(PacketPtr pkt);
202 void recvRespRetry();
206 #endif //__SIMPLE_MEMORY_HH__