src/mem/simple_mem.hh

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Andreas Hansson
  42  */
  43
  44 /**
  45  * @file
  46  * SimpleMemory declaration
  47  */
  48
  49 #ifndef __MEM_SIMPLE_MEMORY_HH__
  50 #define __MEM_SIMPLE_MEMORY_HH__
  51
  52 #include <list>
  53
  54 #include "mem/abstract_mem.hh"
  55 #include "mem/port.hh"
  56 #include "params/SimpleMemory.hh"
  57
  58 /**
  59  * The simple memory is a basic single-ported memory controller with
  60  * a configurable throughput and latency.
  61  *
  62  * @sa  \ref gem5MemorySystem "gem5 Memory System"
  63  */
  64 class SimpleMemory : public AbstractMemory
  65 {
  66
  67   private:
  68
  69     /**
  70      * A deferred packet stores a packet along with its scheduled
  71      * transmission time
  72      */
  73     class DeferredPacket
  74     {
  75
  76       public:
  77
  78         const Tick tick;
  79         const PacketPtr pkt;
  80
  81         DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
  82         { }
  83     };
  84
  85     class MemoryPort : public SlavePort
  86     {
  87
  88       private:
  89
  90         SimpleMemory& memory;
  91
  92       public:
  93
  94         MemoryPort(const std::string& _name, SimpleMemory& _memory);
  95
  96       protected:
  97
  98         Tick recvAtomic(PacketPtr pkt);
  99
 100         void recvFunctional(PacketPtr pkt);
 101
 102         bool recvTimingReq(PacketPtr pkt);
 103
 104         void recvRespRetry();
 105
 106         AddrRangeList getAddrRanges() const;
 107
 108     };
 109
 110     MemoryPort port;
 111
 112     /**
 113      * Latency from that a request is accepted until the response is
 114      * ready to be sent.
 115      */
 116     const Tick latency;
 117
 118     /**
 119      * Fudge factor added to the latency.
 120      */
 121     const Tick latency_var;
 122
 123     /**
 124      * Internal (unbounded) storage to mimic the delay caused by the
 125      * actual memory access. Note that this is where the packet spends
 126      * the memory latency.
 127      */
 128     std::list<DeferredPacket> packetQueue;
 129
 130     /**
 131      * Bandwidth in ticks per byte. The regulation affects the
 132      * acceptance rate of requests and the queueing takes place after
 133      * the regulation.
 134      */
 135     const double bandwidth;
 136
 137     /**
 138      * Track the state of the memory as either idle or busy, no need
 139      * for an enum with only two states.
 140      */
 141     bool isBusy;
 142
 143     /**
 144      * Remember if we have to retry an outstanding request that
 145      * arrived while we were busy.
 146      */
 147     bool retryReq;
 148
 149     /**
 150      * Remember if we failed to send a response and are awaiting a
 151      * retry. This is only used as a check.
 152      */
 153     bool retryResp;
 154
 155     /**
 156      * Release the memory after being busy and send a retry if a
 157      * request was rejected in the meanwhile.
 158      */
 159     void release();
 160
 161     EventFunctionWrapper releaseEvent;
 162
 163     /**
 164      * Dequeue a packet from our internal packet queue and move it to
 165      * the port where it will be sent as soon as possible.
 166      */
 167     void dequeue();
 168
 169     EventFunctionWrapper dequeueEvent;
 170
 171     /**
 172      * Detemine the latency.
 173      *
 174      * @return the latency seen by the current packet
 175      */
 176     Tick getLatency() const;
 177
 178     /**
 179      * Upstream caches need this packet until true is returned, so
 180      * hold it for deletion until a subsequent call
 181      */
 182     std::unique_ptr<Packet> pendingDelete;
 183
 184   public:
 185
 186     SimpleMemory(const SimpleMemoryParams *p);
 187
 188     DrainState drain() override;
 189
 190     BaseSlavePort& getSlavePort(const std::string& if_name,
 191                                 PortID idx = InvalidPortID) override;
 192     void init() override;
 193
 194   protected:
 195
 196     Tick recvAtomic(PacketPtr pkt);
 197
 198     void recvFunctional(PacketPtr pkt);
 199
 200     bool recvTimingReq(PacketPtr pkt);
 201
 202     void recvRespRetry();
 203
 204 };
 205
 206 #endif //__MEM_SIMPLE_MEMORY_HH__