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40 * Authors: Ron Dreslinski
46 * SimpleMemory declaration
49 #ifndef __SIMPLE_MEMORY_HH__
50 #define __SIMPLE_MEMORY_HH__
52 #include "mem/abstract_mem.hh"
53 #include "mem/tport.hh"
54 #include "params/SimpleMemory.hh"
57 * The simple memory is a basic single-ported memory controller with
58 * an configurable throughput and latency, potentially with a variance
59 * added to the latter. It uses a QueueSlavePort to avoid dealing with
60 * the flow control of sending responses.
61 * @sa \ref gem5MemorySystem "gem5 Memory System"
63 class SimpleMemory : public AbstractMemory
68 class MemoryPort : public QueuedSlavePort
73 /// Queue holding the response packets
74 SlavePacketQueue queueImpl;
79 MemoryPort(const std::string& _name, SimpleMemory& _memory);
83 Tick recvAtomic(PacketPtr pkt);
85 void recvFunctional(PacketPtr pkt);
87 bool recvTimingReq(PacketPtr pkt);
89 AddrRangeList getAddrRanges() const;
98 /// Bandwidth in ticks per byte
99 const double bandwidth;
102 * Track the state of the memory as either idle or busy, no need
103 * for an enum with only two states.
108 * Remember if we have to retry an outstanding request that
109 * arrived while we were busy.
114 * Release the memory after being busy and send a retry if a
115 * request was rejected in the meanwhile.
119 EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
121 /** @todo this is a temporary workaround until the 4-phase code is
122 * committed. upstream caches needs this packet until true is returned, so
123 * hold onto it for deletion until a subsequent call
125 std::vector<PacketPtr> pendingDelete;
129 SimpleMemory(const SimpleMemoryParams *p);
130 virtual ~SimpleMemory() { }
132 unsigned int drain(DrainManager *dm);
134 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
135 PortID idx = InvalidPortID);
140 Tick doAtomicAccess(PacketPtr pkt);
141 void doFunctionalAccess(PacketPtr pkt);
142 bool recvTimingReq(PacketPtr pkt);
143 Tick calculateLatency(PacketPtr pkt);
147 #endif //__SIMPLE_MEMORY_HH__