src/mem/tport.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "mem/tport.hh"
  42 #include "sim/sim_object.hh"
  43
  44 SimpleTimingPort::SimpleTimingPort(const std::string& _name,
  45                                    SimObject* _owner) :
  46     QueuedResponsePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
  47 {
  48 }
  49
  50 void
  51 SimpleTimingPort::recvFunctional(PacketPtr pkt)
  52 {
  53     if (!respQueue.trySatisfyFunctional(pkt)) {
  54         // do an atomic access and throw away the returned latency
  55         recvAtomic(pkt);
  56     }
  57 }
  58
  59 bool
  60 SimpleTimingPort::recvTimingReq(PacketPtr pkt)
  61 {
  62     // the SimpleTimingPort should not be used anywhere where there is
  63     // a need to deal with snoop responses and their flow control
  64     // requirements
  65     if (pkt->cacheResponding())
  66         panic("SimpleTimingPort should never see packets with the "
  67               "cacheResponding flag set\n");
  68
  69     bool needsResponse = pkt->needsResponse();
  70     Tick latency = recvAtomic(pkt);
  71     // turn packet around to go back to requestor if response expected
  72     if (needsResponse) {
  73         // recvAtomic() should already have turned packet into
  74         // atomic response
  75         assert(pkt->isResponse());
  76         schedTimingResp(pkt, curTick() + latency);
  77     } else {
  78         // queue the packet for deletion
  79         pendingDelete.reset(pkt);
  80     }
  81
  82     return true;
  83 }