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44 #ifndef __MEM_TPORT_HH__
45 #define __MEM_TPORT_HH__
50 * Declaration of SimpleTimingPort.
53 #include "mem/qport.hh"
56 * The simple timing port uses a queued port to implement
57 * recvFunctional and recvTimingReq through recvAtomic. It is always a
60 class SimpleTimingPort : public QueuedSlavePort
66 * The packet queue used to store outgoing responses. Note that
67 * the queue is made private and that we avoid overloading the
68 * name used in the QueuedSlavePort. Access is provided through
69 * the queue reference in the base class.
71 SlavePacketQueue queueImpl;
75 /** Implemented using recvAtomic(). */
76 void recvFunctional(PacketPtr pkt);
78 /** Implemented using recvAtomic(). */
79 bool recvTimingReq(PacketPtr pkt);
81 virtual Tick recvAtomic(PacketPtr pkt) = 0;
84 * @todo this is a temporary workaround until the 4-phase code is committed.
85 * upstream caches need this packet until true is returned, so hold it for
86 * deletion until a subsequent call
88 std::vector<PacketPtr> pendingDelete;
94 * Create a new SimpleTimingPort that relies on a packet queue to
95 * hold responses, and implements recvTimingReq and recvFunctional
96 * through calls to recvAtomic. Once a request arrives, it is
97 * passed to recvAtomic, and in the case of a timing access any
98 * response is scheduled to be sent after the delay of the atomic
101 * @param name port name
102 * @param owner structural owner
104 SimpleTimingPort(const std::string& name, MemObject* owner);
106 virtual ~SimpleTimingPort() { }
110 #endif // __MEM_TPORT_HH__