src/mem/tport.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 #ifndef __MEM_TPORT_HH__
  32 #define __MEM_TPORT_HH__
  33
  34 /**
  35  * @file
  36  *
  37  * Declaration of SimpleTimingPort.
  38  */
  39
  40 #include "mem/port.hh"
  41 #include "sim/eventq.hh"
  42 #include <list>
  43 #include <string>
  44
  45 /**
  46  * A simple port for interfacing objects that basically have only
  47  * functional memory behavior (e.g. I/O devices) to the memory system.
  48  * Both timing and functional accesses are implemented in terms of
  49  * atomic accesses.  A derived port class thus only needs to provide
  50  * recvAtomic() to support all memory access modes.
  51  *
  52  * The tricky part is handling recvTiming(), where the response must
  53  * be scheduled separately via a later call to sendTiming().  This
  54  * feature is handled by scheduling an internal event that calls
  55  * sendTiming() after a delay, and optionally rescheduling the
  56  * response if it is nacked.
  57  */
  58 class SimpleTimingPort : public Port
  59 {
  60   protected:
  61     /** A list of outgoing timing response packets that haven't been
  62      * serviced yet. */
  63     std::list<PacketPtr> transmitList;
  64
  65     /**
  66      * This class is used to implemented sendTiming() with a delay. When
  67      * a delay is requested a new event is created. When the event time
  68      * expires it attempts to send the packet. If it cannot, the packet
  69      * is pushed onto the transmit list to be sent when recvRetry() is
  70      * called. */
  71     class SendEvent : public Event
  72     {
  73         SimpleTimingPort *port;
  74         PacketPtr packet;
  75
  76       public:
  77         SendEvent(SimpleTimingPort *p, PacketPtr pkt, Tick t)
  78             : Event(&mainEventQueue), port(p), packet(pkt)
  79         { setFlags(AutoDelete); schedule(curTick + t); }
  80
  81         virtual void process();
  82
  83         virtual const char *description()
  84         { return "Future scheduled sendTiming event"; }
  85     };
  86
  87
  88     /** Number of timing requests that are emulating the device timing before
  89      * attempting to end up on the bus.
  90      */
  91     int outTiming;
  92
  93     /** If we need to drain, keep the drain event around until we're done
  94      * here.*/
  95     Event *drainEvent;
  96
  97     /** Schedule a sendTiming() event to be called in the future. */
  98     void sendTimingLater(PacketPtr pkt, Tick time)
  99     { outTiming++; new SendEvent(this, pkt, time); }
 100
 101     /** This function is notification that the device should attempt to send a
 102      * packet again. */
 103     virtual void recvRetry();
 104
 105     /** Implemented using recvAtomic(). */
 106     void recvFunctional(PacketPtr pkt);
 107
 108     /** Implemented using recvAtomic(). */
 109     bool recvTiming(PacketPtr pkt);
 110
 111     /**
 112      * Simple ports generally don't care about any status
 113      * changes... can always override this in cases where that's not
 114      * true. */
 115     virtual void recvStatusChange(Status status) { }
 116
 117
 118   public:
 119
 120     SimpleTimingPort(std::string pname)
 121         : Port(pname), outTiming(0), drainEvent(NULL)
 122     {}
 123
 124     /** Hook for draining timing accesses from the system.  The
 125      * associated SimObject's drain() functions should be implemented
 126      * something like this when this class is used:
 127      \code
 128           PioDevice::drain(Event *de)
 129           {
 130               unsigned int count;
 131               count = SimpleTimingPort->drain(de);
 132               if (count)
 133                   changeState(Draining);
 134               else
 135                   changeState(Drained);
 136               return count;
 137           }
 138      \endcode
 139     */
 140     unsigned int drain(Event *de);
 141 };
 142
 143 #endif // __MEM_TPORT_HH__